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HD66766R
Rev. 1.0-1 / September 2002
HD66766R
(132 x 176-dot Graphics LCD Controller/Driver for 65K Colors)
Rev.1.0-1 September, 2002
Description
The HD66766R, color-graphics LCD controller and driver LSI, displays 132-by-176-dot graphics for 65K STN colors. A 16-bit high-speed bus interface and high-speed RAM write function enable efficient data transfer and high-speed rewriting of data to the graphics RAM. The HD66766R has various functions for reducing the power consumption of a LCD system, such as low-voltage operation of 2.2 V/min., a step-up circuit to generate a maximum of 12-times the LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-resistors. Combining these hardware functions with software functions, such as a partial display with low-duty drive and standby and sleep modes, allows precise power control. The HD66766R is suitable for any mid-sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular phones supporting a WWW browser, bi-directional pagers, and small PDAs.
Features
* * * * * * 132RGB x 176-dot graphics display LCD controller/driver for 65K STN colors low voltage drive and flickerless PWM grayscale drive 16-/8-bit high-speed bus interface and Clock Synchronized Serial Interface ( SPI ) High-speed burst-RAM write function Writing to a window-RAM address area by using a window-address function Bit-operation functions for graphics processing: - Write-data mask function in bit units. - Logical operation in pixel unit and conditional write function.
1
HD66766R
*
Rev. 1.0-1 / September 2002
Various color-display control functions - 65K out of 140K possible colors can be displayed at the same time (grayscale palette incorporated) - Vertical scroll display function in raster-row units - Partial LCD drive of two screens in any position Low-power operation supports: - Vcc = 2.2 to 3.6 V (low-voltage) - Common driving voltage = 8 to 44 V - Segment driving voltage = 2 to 4 V - VOUT power voltage = 4.0V to 5.75 V - Power-save functions such as the standby mode and sleep mode - Internal power supply circuit - Programmable drive duty ratios (1/8-1/176) and bias values (1/2-1/13) displayed on LCD - Maximum 12-times step-up circuit for liquid crystal drives voltage and voltage inverting circuit - 128-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors Internal RAM capacity: 46,464 bytes 396-segment x 176-common liquid crystal display driver n-raster-row AC liquid-crystal drive (C-pattern waveform drive) Internal oscillation and hardware reset Shift change of segment and common drivers COM positioned on both sides in one chip for COG
*
* * * * * *
Type Name
Types HCD667A66RBP HCD667B66RBP External Dimensions Au-bumped chip straight bump Au-bumped chip laced bump
Difference between HCD667x66R and HCD667x66
Table 1 Difference Pad arrangement HCD667x66R Pad No. Pad Name 63 Vcc 63 Vcc 64 Vcc 66 Vcc 67 AVcc 68 AVcc 69 AVcc 70 AVcc HCD667x66 Pad No. Pad Name 63 Vcc 63 Vcc 64 Vcc 66 Vcc 67 Vcc 68 Vcc 69 Vcc 70 Vcc
2
HD66766R
nChip size: 18.65mmx2.63mm nChip thickness: 400um (typ.) nPad coordinate: Pad center nCoordinate origin: Chip center nAu bump size: (1) 80m x 80m DUMMY1, DUMMY2, RESET1*~ RESET3*, DUMMY10, DUMMY11 DUMMY12, DUMMY13 (2) 23m x 140m COM1 ~ COM176 SEG1 ~ SEG396 nAu bump pitch: Refer to pad coordinate nAu bump hight: 15m(typ.) n Numbers in the figure corresponds to the number of pad coordinate. n Alignment mark (1) Arrangement: Two places ** @@ Coordinate (X, Y) = (9000, -1121)
100m 50 30
NO.1
Rev. 1.0-1 / September 2002
COM99 COM101 COM103 COM105 COMP COM3 COM5 COM7
g HD66766R PAD Arrangement (Straight Output Arrangement)
NO.666
* DUMMY13 * * * * COM107 COM109 COM111 COM113 DUMMY1 * DUMMY2 * RESET1* * CEP * CEP * CEM * CEM * VCL * VCL * VCL * VCL * VCH * VCH * VCH * VCH * C24+ * C24+ * C24- * C24- * C23+ * C23+ * C23- * C23- * C22+ * C22+ * C22- * C22- * C21+ * C21+ * C21- * C21- * VCI2 * VCI2 * VCI2 * VCI2 * GNDDUM1 * **** ****
* * * * * * * *
COM169 COM171 COM173 COM175 SEG1 SEG2 SEG3 SEG4
HD667A66R
TypeCode
30
40
30
(2-a) Coordinate (X, Y) = (-9094, 1145)
50m
(2-b) Coordinate (X, Y) = (9094, 1145)
20
50m
(3-a) Coordinate (X, Y) = (-9004, 1145)
5 10 25 25 10 5 10 5
80m 70m
GNDDUM4 * DB15 * DB14 * DB13 * DB12 * DB11 * DB10 * DB9 * DB8 * GNDDUM5 * DB7 * DB6 * DB5 * DB4 * DB3 * DB2 * DB1/SDO * DB0/SDI * GNDDUM6 * RW/RD* * E/WR*/SCL * GNDDUM7 * RS * CS* * VCC * VCC * VCC * VCC * AVCC * AVCC * AVCC * AVCC * AGND * AGND * GND * GND * GND * GND * AGND * AGND * RESET2* * OSC2 * OSC1 * GNDDUM8 * IM2 * VCCDUM1 * IM1 * GNDDUM9 * IM0/ID * VCCDUM2 * TEST2 * TEST1 * GNDDUM10 * DUMMY3 * DUMMY9 * VREFL * VREFL * BIASC * BIASC * VREFM * VREFM * VM * C12- * C12- * C12- * C12- * C11+ * C11+ * C11+ * C11+ * C11- * C11- * C11- * C11- * VCIOUT * VCIOUT * VCIOUT * VCIOUT * VCI1 * VCI1 * VCI1 * VCI1 * VCCDUM3 * VCCDUM4 * RESET3* * DUMMY10 * DUMMY11 *
100m
50
30
40
HD667A66R Straight (Top View)
Y X
70m 80m
5 10
25
25
(3-b) Coordinate (X, Y) = (9004, 1145)
10 25 25 10 10
* * * * * * * *
SEG393 SEG394 SEG395 SEG396 COM176 COM174 COM172 COM170
70m
10
25
25
70m
* * * * **** COM2 COM4 COM6 COM8 **** COM100 COM102 COM104 COM106
COM114 COM112 COM110 COM108
* DUMMY12
NO.145
NO.199
Figure 1 PAD arrangement (Straight)
3
HD66766R
Table 2
HD66766R PAD Coordinate (Straight)(No.1) No. pad name X Y No. pad name 1 DUMMY1 -9193 -1168 81 OSC1 2 DUMMY2 -8835 -1168 82 GNDDUM8 3 RESET1* -8678 -1168 83 IM2 4 CEP -8498 -1168 84 VCCDUM1 5 CEP -8398 -1168 85 IM1 6 CEM -8298 -1168 86 GNDDUM9 7 CEM -8198 -1168 87 IM0/ID 8 VCL -8018 -1168 88 VCCDUM2 9 VCL -7918 -1168 89 TEST2 10 VCL -7818 -1168 90 TEST1 11 VCL -7718 -1168 91 GNDDUM10 12 VCH -7538 -1168 92 DUMMY3 13 VCH -7438 -1168 93 DUMMY4 14 VCH -7338 -1168 94 DUMMY5 15 VCH -7237 -1168 95 DUMMY6 16 C24+ -7057 -1168 96 DUMMY7 17 C24+ -6957 -1168 97 DUMMY8 18 C24-6857 -1168 98 DUMMY9 19 C24-6757 -1168 99 VREFL 20 C23+ -6657 -1168 100 VREFL 21 C23+ -6557 -1168 101 BIASC 22 C23-6457 -1168 102 BIASC 23 C23-6357 -1168 103 VREFM 24 C22+ -6257 -1168 104 VREFM 25 C22+ -6157 -1168 105 VM 26 C22-6057 -1168 106 VM 27 C22-5957 -1168 107 VM 28 C21+ -5856 -1168 108 VM 29 C21+ -5756 -1168 109 VSH 30 C21-5576 -1168 110 VSH 31 C21-5476 -1168 111 VSH 32 VCI2 -5376 -1168 112 VSH 33 VCI2 -5276 -1168 113 VOUT 34 VCI2 -5176 -1168 114 VOUT 35 VCI2 -5076 -1168 115 VOUT 36 GNDDUM1 -4896 -1168 116 VOUT 37 GNDDUM2 -4796 -1168 117 C12+ 38 GNDDUM3 -4696 -1168 118 C12+ 39 GNDDUM4 -4596 -1168 119 C12+ 40 DB15 -4416 -1168 120 C12+ 41 DB14 -4259 -1168 121 C1242 DB13 -4103 -1168 122 C1243 DB12 -3946 -1168 123 C1244 DB11 -3789 -1168 124 C1245 DB10 -3633 -1168 125 C11+ 46 DB9 -3476 -1168 126 C11+ 47 DB8 -3320 -1168 127 C11+ 48 GNDDUM5 -3163 -1168 128 C11+ 49 DB7 -3006 -1168 129 C1150 DB6 -2850 -1168 130 C1151 DB5 -2693 -1168 131 C1152 DB4 -2537 -1168 132 C1153 DB3 -2380 -1168 133 VCIOUT 54 DB2 -2223 -1168 134 VCIOUT 55 DB1/SDO -2067 -1168 135 VCIOUT 56 DB0/SDI -1910 -1168 136 VCIOUT 57 GNDDUM6 -1754 -1168 137 VCI1 58 RW/RD* -1597 -1168 138 VCI1 59 E/WR*/SCL -1440 -1168 139 VCI1 60 GNDDUM7 -1284 -1168 140 VCI1 61 RS -1127 -1168 141 VCCDUM3 62 CS* -971 -1168 142 VCCDUM4 63 VCC -791 -1168 143 RESET3* 64 VCC -690 -1168 144 DUMMY10 65 VCC -590 -1168 145 DUMMY11 66 VCC -490 -1168 146 COM2 67 AVCC -390 -1168 147 COM4 68 AVCC -290 -1168 148 COM6 69 AVCC -190 -1168 149 COM8 70 AVCC -90 -1168 150 COM10 71 AGND 90 -1168 151 COM12 72 AGND 190 -1168 152 COM14 73 GND 290 -1168 153 COM16 74 GND 390 -1168 154 COM18 75 GND 490 -1168 155 COM20 76 GND 590 -1168 156 COM22 77 AGND 690 -1168 157 COM24 78 AGND 791 -1168 158 COM26 79 RESET2* 971 -1168 159 COM28 80 OSC2 1127 -1168 160 COM30 X 1284 1440 1597 1754 1910 2067 2223 2380 2537 2693 2850 3030 3130 3230 3330 3430 3530 3630 3810 3910 4010 4110 4211 4311 4411 4511 4611 4711 4811 4911 5011 5111 5291 5391 5491 5592 5772 5872 5972 6072 6172 6272 6372 6472 6572 6672 6772 6872 6972 7073 7173 7273 7453 7553 7653 7753 7933 8033 8133 8233 8413 8513 8693 8850 9193 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 Y -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -1168 -981 -943 -905 -867 -829 -791 -753 -715 -677 -639 -601 -563 -525 -487 -449 No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 pad name COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 COM64 COM66 COM68 COM70 COM72 COM74 COM76 COM78 COM80 COM82 COM84 COM86 COM88 COM90 COM92 COM94 COM96 COM98 COM100 COM102 COM104 COM106 DUMMY12 COM108 COM110 COM112 COM114 COM116 COM118 COM120 COM122 COM124 COM126 COM128 COM130 COM132 COM134 COM136 COM138 COM140 COM142 COM144 COM146 COM148 COM150 COM152 COM154 COM156 COM158 COM160 COM162 COM164 COM166 COM168 COM170 COM172 COM174 COM176 SEG396 SEG395 SEG394 SEG393 SEG392 SEG391 X 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9155 9193 8892 8854 8816 8778 8740 8702 8664 8626 8588 8550 8512 8474 8436 8398 8360 8322 8284 8246 8208 8170 8132 8094 8056 8018 7980 7942 7904 7866 7828 7790 7752 7714 7676 7638 7600 7524 7486 7448 7410 7372 7334
Rev. 1.0-1 / September 2002
Y -411 -373 -335 -297 -259 -221 -183 -145 -107 -69 -31 7 45 83 121 159 197 235 273 311 349 387 425 463 501 539 577 615 653 691 729 767 805 843 881 919 957 995 1183 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 pad name SEG390 SEG389 SEG388 SEG387 SEG386 SEG385 SEG384 SEG383 SEG382 SEG381 SEG380 SEG379 SEG378 SEG377 SEG376 SEG375 SEG374 SEG373 SEG372 SEG371 SEG370 SEG369 SEG368 SEG367 SEG366 SEG365 SEG364 SEG363 SEG362 SEG361 SEG360 SEG359 SEG358 SEG357 SEG356 SEG355 SEG354 SEG353 SEG352 SEG351 SEG350 SEG349 SEG348 SEG347 SEG346 SEG345 SEG344 SEG343 SEG342 SEG341 SEG340 SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 SEG315 SEG314 SEG313 SEG312 SEG311 X 7296 7258 7220 7182 7144 7106 7068 7030 6992 6954 6916 6878 6840 6802 6764 6726 6688 6650 6612 6574 6536 6498 6460 6422 6384 6346 6308 6270 6232 6194 6156 6118 6080 6042 6004 5966 5928 5890 5852 5814 5776 5738 5700 5662 5624 5586 5548 5510 5472 5434 5396 5358 5320 5282 5244 5206 5168 5130 5092 5054 5016 4978 4940 4902 4864 4826 4788 4750 4712 4674 4636 4598 4560 4522 4484 4446 4408 4370 4332 4294 Y 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 No. 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 pad name SEG310 SEG309 SEG308 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 SEG299 SEG298 SEG297 SEG296 SEG295 SEG294 SEG293 SEG292 SEG291 SEG290 SEG289 SEG288 SEG287 SEG286 SEG285 SEG284 SEG283 SEG282 SEG281 SEG280 SEG279 SEG278 SEG277 SEG276 SEG275 SEG274 SEG273 SEG272 SEG271 SEG270 SEG269 SEG268 SEG267 SEG266 SEG265 SEG264 SEG263 SEG262 SEG261 SEG260 SEG259 SEG258 SEG257 SEG256 SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 SEG248 SEG247 SEG246 SEG245 SEG244 SEG243 SEG242 SEG241 SEG240 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 SEG231 X 4256 4218 4180 4142 4104 4066 4028 3990 3952 3914 3876 3838 3800 3762 3724 3686 3648 3610 3572 3534 3496 3458 3420 3382 3344 3306 3268 3230 3192 3154 3116 3078 3040 3002 2964 2926 2888 2850 2812 2774 2736 2698 2660 2622 2584 2546 2508 2470 2432 2394 2356 2318 2280 2242 2204 2166 2128 2090 2052 2014 1976 1938 1900 1862 1824 1786 1748 1710 1672 1634 1596 1558 1520 1482 1444 1406 1368 1330 1292 1254 Y 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145
4
HD66766R
Table 2 cont.
HD66766R PAD Coordinate *i Straight*j (No.2) No. pad name X Y No. pad name 401 SEG230 1216 1145 481 SEG150 402 SEG229 1178 1145 482 SEG149 403 SEG228 1140 1145 483 SEG148 404 SEG227 1102 1145 484 SEG147 405 SEG226 1064 1145 485 SEG146 406 SEG225 1026 1145 486 SEG145 407 SEG224 988 1145 487 SEG144 408 SEG223 950 1145 488 SEG143 409 SEG222 912 1145 489 SEG142 410 SEG221 874 1145 490 SEG141 411 SEG220 836 1145 491 SEG140 412 SEG219 798 1145 492 SEG139 413 SEG218 760 1145 493 SEG138 414 SEG217 722 1145 494 SEG137 415 SEG216 684 1145 495 SEG136 416 SEG215 646 1145 496 SEG135 417 SEG214 608 1145 497 SEG134 418 SEG213 570 1145 498 SEG133 419 SEG212 532 1145 499 SEG132 420 SEG211 494 1145 500 SEG131 421 SEG210 456 1145 501 SEG130 422 SEG209 418 1145 502 SEG129 423 SEG208 380 1145 503 SEG128 424 SEG207 342 1145 504 SEG127 425 SEG206 304 1145 505 SEG126 426 SEG205 266 1145 506 SEG125 427 SEG204 228 1145 507 SEG124 428 SEG203 190 1145 508 SEG123 429 SEG202 152 1145 509 SEG122 430 SEG201 114 1145 510 SEG121 431 SEG200 76 1145 511 SEG120 432 SEG199 38 1145 512 SEG119 433 SEG198 -38 1145 513 SEG118 434 SEG197 -76 1145 514 SEG117 435 SEG196 -114 1145 515 SEG116 436 SEG195 -152 1145 516 SEG115 437 SEG194 -190 1145 517 SEG114 438 SEG193 -228 1145 518 SEG113 439 SEG192 -266 1145 519 SEG112 440 SEG191 -304 1145 520 SEG111 441 SEG190 -342 1145 521 SEG110 442 SEG189 -380 1145 522 SEG109 443 SEG188 -418 1145 523 SEG108 444 SEG187 -456 1145 524 SEG107 445 SEG186 -494 1145 525 SEG106 446 SEG185 -532 1145 526 SEG105 447 SEG184 -570 1145 527 SEG104 448 SEG183 -608 1145 528 SEG103 449 SEG182 -646 1145 529 SEG102 450 SEG181 -684 1145 530 SEG101 451 SEG180 -722 1145 531 SEG100 452 SEG179 -760 1145 532 SEG99 453 SEG178 -798 1145 533 SEG98 454 SEG177 -836 1145 534 SEG97 455 SEG176 -874 1145 535 SEG96 456 SEG175 -912 1145 536 SEG95 457 SEG174 -950 1145 537 SEG94 458 SEG173 -988 1145 538 SEG93 459 SEG172 -1026 1145 539 SEG92 460 SEG171 -1064 1145 540 SEG91 461 SEG170 -1102 1145 541 SEG90 462 SEG169 -1140 1145 542 SEG89 463 SEG168 -1178 1145 543 SEG88 464 SEG167 -1216 1145 544 SEG87 465 SEG166 -1254 1145 545 SEG86 466 SEG165 -1292 1145 546 SEG85 467 SEG164 -1330 1145 547 SEG84 468 SEG163 -1368 1145 548 SEG83 469 SEG162 -1406 1145 549 SEG82 470 SEG161 -1444 1145 550 SEG81 471 SEG160 -1482 1145 551 SEG80 472 SEG159 -1520 1145 552 SEG79 473 SEG158 -1558 1145 553 SEG78 474 SEG157 -1596 1145 554 SEG77 475 SEG156 -1634 1145 555 SEG76 476 SEG155 -1672 1145 556 SEG75 477 SEG154 -1710 1145 557 SEG74 478 SEG153 -1748 1145 558 SEG73 479 SEG152 -1786 1145 559 SEG72 480 SEG151 -1824 1145 560 SEG71 X -1862 -1900 -1938 -1976 -2014 -2052 -2090 -2128 -2166 -2204 -2242 -2280 -2318 -2356 -2394 -2432 -2470 -2508 -2546 -2584 -2622 -2660 -2698 -2736 -2774 -2812 -2850 -2888 -2926 -2964 -3002 -3040 -3078 -3116 -3154 -3192 -3230 -3268 -3306 -3344 -3382 -3420 -3458 -3496 -3534 -3572 -3610 -3648 -3686 -3724 -3762 -3800 -3838 -3876 -3914 -3952 -3990 -4028 -4066 -4104 -4142 -4180 -4218 -4256 -4294 -4332 -4370 -4408 -4446 -4484 -4522 -4560 -4598 -4636 -4674 -4712 -4750 -4788 -4826 -4864 Y 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 No. 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 pad name SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM175 COM173 COM171 COM169 COM167 COM165 COM163 COM161 COM159 COM157 X -4902 -4940 -4978 -5016 -5054 -5092 -5130 -5168 -5206 -5244 -5282 -5320 -5358 -5396 -5434 -5472 -5510 -5548 -5586 -5624 -5662 -5700 -5738 -5776 -5814 -5852 -5890 -5928 -5966 -6004 -6042 -6080 -6118 -6156 -6194 -6232 -6270 -6308 -6346 -6384 -6422 -6460 -6498 -6536 -6574 -6612 -6650 -6688 -6726 -6764 -6802 -6840 -6878 -6916 -6954 -6992 -7030 -7068 -7106 -7144 -7182 -7220 -7258 -7296 -7334 -7372 -7410 -7448 -7486 -7524 -7600 -7638 -7676 -7714 -7752 -7790 -7828 -7866 -7904 -7942
Rev. 1.0-1 / September 2002
Y 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 No. 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 pad name COM155 COM153 COM151 COM149 COM147 COM145 COM143 COM141 COM139 COM137 COM135 COM133 COM131 COM129 COM127 COM125 COM123 COM121 COM119 COM117 COM115 COM113 COM111 COM109 COM107 DUMMY13 COM105 COM103 COM101 COM99 COM97 COM95 COM93 COM91 COM89 COM87 COM85 COM83 COM81 COM79 COM77 COM75 COM73 COM71 COM69 COM67 COM65 COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 X -7980 -8018 -8056 -8094 -8132 -8170 -8208 -8246 -8284 -8322 -8360 -8398 -8436 -8474 -8512 -8550 -8588 -8626 -8664 -8702 -8740 -8778 -8816 -8854 -8892 -9193 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 -9155 Y X Y Alignment mark 1145 -9000 -1121 Cross 1145 9000 -1121 1145 Circle(Positive) -9094 1145 1145 Circle(Negative) 9094 1145 1145 L (Positive) -9004 1145 1145 9004 1145 L (Negative) 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1145 1183 995 957 919 881 843 805 767 729 691 653 615 577 539 501 463 425 387 349 311 273 235 197 159 121 83 45 7 -31 -69 -107 -145 -183 -221 -259 -297 -335 -373 -411 -449 -487 -525 -563 -601 -639 -677 -715 -753 -791 -829 -867 -905 -943 -981
5
HD66766R
n Chip size: 18.65mmx2.63mm n Chip thickness: 400m (typ.) n Pad coordinate: Pad center n Coordinate origin: Chip center n Au bump size: (1) 80mx80m DUMMY1, DUMMY2, RESET1*~ RESET3*, DUMMY10, DUMMY11 DUMMY12, DUMMY13 (2) 38mx63m COM1~COM176 SEG1~SEG396 n Au bump pitch: Refer to pad coordinate n Au bump hight: 15m(typ.) n Numbers in the figure correspond to the number of pad coordinate. n Alignment mark (1) Arrangement: Two places ** @Coordinate (X, Y) = (9000, -1121) @
100m 50 30
Rev. 1.0-1 / September 2002
COMP COM3 COM5 COM7
g HD66766R PAD Arrangement (LacedOutput Arrangement)
NO.1
DUMMY1 * DUMMY2 * RESET1* * CEP * CEP * CEM * CEM * VCL * VCL * VCL * VCL * VCH * VCH * VCH * VCH * C24+ * C24+ * C24- * C24- * C23+ * C23+ * C23- * C23- * C22+ * C22+ * C22- * C22- * C21+ * C21+ * C21- * C21- * VCI2 * VCI2 * VCI2 * VCI2 * GNDDUM1 * GNDDUM4 * DB15 * DB14 * DB13 * DB12 * DB11 * DB10 * DB9 * DB8 * GNDDUM5 * DB7 * DB6 * DB5 * DB4 * DB3 * DB2 * DB1/SDO * DB0/SDI * GNDDUM6 * RW/RD* * E/WR*/SCL * GNDDUM7 * RS * CS* * VCC * VCC * VCC * VCC * AVCC * AVCC * AVCC * AVCC * AGND * AGND * GND * GND * GND * GND * AGND * AGND * RESET2* * OSC2 * OSC1 * GNDDUM8 * IM2 * VCCDUM1 * IM1 * GNDDUM9 * IM0/ID * VCCDUM2 * TEST2 * TEST1 * GNDDUM10 * DUMMY3 * DUMMY9 * VREFL * VREFL * BIASC * BIASC * VREFM * VREFM * VM * VM * VM * VM * VSH * VSH * VSH * VSH * VOUT * VOUT * VOUT * VOUT * OSC0 * OSC1 * GNDDUM9 * C12+ * C12- * C12- * C12- * C12- * C11+ * C11+ * C11+ * C11+ * C11- * C11- * C11- * C11- * VCIOUT * VCIOUT * VCIOUT * VCIOUT * VCI1 * VCI1 * VCI1 * VCI1 * VCCDUM3 * VCCDUM4 * RESET3* * DUMMY10 * * DUMMY11 * * * * * * * * * DUMMY12 COM99 COM101 COM103 COM105
NO.666
* DUMMY13 * * * COM107 COM109 * COM111 COM113
* *
* * *
* *
*
* *
COM169 * COM171 COM173 * COM175 * SEG1 * SEG2 * SEG3 * SEG4
HD667B66R
TypeCode
HD667B66R Laced (Top View)
Y X
100 m
50
30
40
30
(2-a) Coordinate (X, Y) = (-9094, 1145)
50m
(2-b) Coordinate (X, Y) = (9094, 1145)
20
50m
(3-a) Coordinate (X, Y) = (-9004, 1145)
5 10 25 25 10 5 10 5 80m 70m 70m 80m 5 10 25 25
30
40
(3-b) Coordinate (X, Y) = (9004, 1145)
10 25 25 10 10
* SEG393 SEG394 * SEG395 * SEG396 * COM176 * COM174 * COM172 * COM170 *
70m
10
25
25
* *
70m
COM114 * COM112 COM110 * COM108
COM2 COM4 COM6 COM8
NO.145
COM100 COM102 COM104 COM106
NO.199
Figure 2 PAD arrangement (Laced)
6
HD66766R
Rev. 1.0-1 / September 2002
Table 3 HD66766R PAD Coordinate (Laced)(No.1) No. pad nameX Y No. pad nameX Y No.pad name Y No.pad name Y No.pad name Y X X X 1DUMMY1 -1168 81 -9193 OSC1 1284 -1168161 COM32 9108 -411 241 SEG390 7296 1098321 SEG31042561098 2DUMMY2 -1168 82 -8835 GNDDUM8 -1168162 1440 COM34 9201 -373 242 SEG389 7258 1191322 SEG30942181191 3RESET1* -8678 -1168 83 IM2 1597 -1168163 COM36 9108 -335 243 SEG388 7220 1098323 SEG30841801098 4CEP -8498 -1168 84 VCCDUM1 -1168164 1754 COM38 9201 -297 244 SEG387 7182 1191324 SEG30741421191 5CEP -8398 -1168 85 IM1 1910 -1168165 COM40 9108 -259 245 SEG386 7144 1098325 SEG30641041098 6CEM -8298 -1168 86 GNDDUM9 -1168166 2067 COM42 9201 -221 246 SEG385 7106 1191326 SEG30540661191 7CEM -8198 -1168 87 IM0/ID 2223 -1168167 COM44 9108 -183 247 SEG384 7068 1098327 SEG30440281098 8VCL -8018 -1168 88 VCCDUM2 -1168168 2380 COM46 9201 -145 248 SEG383 7030 1191328 SEG30339901191 9VCL -7918 -1168 89 TEST2 2537 -1168169 COM48 9108 -107 249 SEG382 6992 1098329 SEG30239521098 10 VCL -7818 -1168 90 TEST1 2693 -1168170 COM50 9201-69 250 SEG381 6954 1191330 SEG30139141191 11 VCL -7718 -1168 91 GNDDUM10 -1168171 2850 COM52 9108-31 251 SEG380 6916 1098331 SEG30038761098 12 VCH -7538 -1168 92 DUMMY3 -1168172 3030 COM54 9201 7 252 SEG379 6878 1191332 SEG29938381191 13 VCH -7438 -1168 93 DUMMY4 -1168173 3130 COM56 9108 45 253 SEG378 6840 1098333 SEG29838001098 14 VCH -7338 -1168 94 DUMMY5 -1168174 3230 COM58 9201 83 254 SEG377 6802 1191334 SEG29737621191 15 VCH -7237 -1168 95 DUMMY6 -1168175 3330 COM60 9108121 255 SEG376 6764 1098335 SEG29637241098 16 C24+ -7057 -1168 96 DUMMY7 -1168176 3430 COM62 9201159 256 SEG375 6726 1191336 SEG29536861191 17 C24+ -6957 -1168 97 DUMMY8 -1168177 3530 COM64 9108197 257 SEG374 6688 1098337 SEG29436481098 18 C24-6857 -1168 98 DUMMY9 -1168178 3630 COM66 9201235 258 SEG373 6650 1191338 SEG29336101191 19 C24-6757 -1168 99 VREFL 3810 -1168179 COM68 9108273 259 SEG372 6612 1098339 SEG29235721098 20 C23+ -6657 -1168100 VREFL 3910 -1168180 COM70 9201311 260 SEG371 6574 1191340 SEG29135341191 21 C23+ -6557 -1168101 BIASC 4010 -1168181 COM72 9108349 261 SEG370 6536 1098341 SEG29034961098 22 C23-6457 -1168102 BIASC 4110 -1168182 COM74 9201387 262 SEG369 6498 1191342 SEG28934581191 23 C23-6357 -1168103 VREFM 4211 -1168183 COM76 9108425 263 SEG368 6460 1098343 SEG28834201098 24 C22+ -6257 -1168104 VREFM 4311 -1168184 COM78 9201463 264 SEG367 6422 1191344 SEG28733821191 25 C22+ -6157 -1168105 VM 4411 -1168185 COM80 9108501 265 SEG366 6384 1098345 SEG28633441098 26 C22-6057 -1168106 VM 4511 -1168186 COM82 9201539 266 SEG365 6346 1191346 SEG28533061191 27 C22-5957 -1168107 VM 4611 -1168187 COM84 9108577 267 SEG364 6308 1098347 SEG28432681098 28 C21+ -5856 -1168108 VM 4711 -1168188 COM86 9201615 268 SEG363 6270 1191348 SEG28332301191 29 C21+ -5756 -1168109 VSH 4811 -1168189 COM88 9108653 269 SEG362 6232 1098349 SEG28231921098 30 C21-5576 -1168110 VSH 4911 -1168190 COM90 9201691 270 SEG361 6194 1191350 SEG28131541191 31 C21-5476 -1168111 VSH 5011 -1168191 COM92 9108729 271 SEG360 6156 1098351 SEG28031161098 32 VCI2 -5376 -1168112 VSH 5111 -1168192 COM94 9201767 272 SEG359 6118 1191352 SEG27930781191 33 VCI2 -5276 -1168113 VOUT 5291 -1168193 COM96 9108805 273 SEG358 6080 1098353 SEG27830401098 34 VCI2 -5176 -1168114 VOUT 5391 -1168194 COM98 9201843 274 SEG357 6042 1191354 SEG27730021191 35 VCI2 -5076 -1168115 VOUT 5491 -1168195 COM1009108881 275 SEG356 6004 1098355 SEG27629641098 36 GNDDUM1 -1168116 -4896 VOUT 5592 -1168196 COM1029201919 276 SEG355 5966 1191356 SEG27529261191 37 GNDDUM2 -1168117 -4796 C12+ 5772 -1168197 COM1049108957 277 SEG354 5928 1098357 SEG27428881098 38 GNDDUM3 -1168118 -4696 C12+ 5872 -1168198 COM1069201995 278 SEG353 5890 1191358 SEG27328501191 39 GNDDUM4 -1168119 -4596 C12+ 5972 -1168199 DUMMY12 1183279 9193 SEG352 5852 1098359 SEG27228121098 40 DB15 -4416 -1168120 C12+ 6072 -1168200 COM1088892 1191280 SEG351 5814 1191360 SEG27127741191 41 DB14 -4259 -1168121 C126172 -1168201 COM1108854 1098281 SEG350 5776 1098361 SEG27027361098 42 DB13 -4103 -1168122 C126272 -1168202 COM1128816 1191282 SEG349 5738 1191362 SEG26926981191 43 DB12 -3946 -1168123 C126372 -1168203 COM1148778 1098283 SEG348 5700 1098363 SEG26826601098 44 DB11 -3789 -1168124 C126472 -1168204 COM1168740 1191284 SEG347 5662 1191364 SEG26726221191 45 DB10 -3633 -1168125 C11+ 6572 -1168205 COM1188702 1098285 SEG346 5624 1098365 SEG26625841098 46 DB9 -3476 -1168126 C11+ 6672 -1168206 COM1208664 1191286 SEG345 5586 1191366 SEG26525461191 47 DB8 -3320 -1168127 C11+ 6772 -1168207 COM1228626 1098287 SEG344 5548 1098367 SEG26425081098 48 GNDDUM5 -1168128 -3163 C11+ 6872 -1168208 COM1248588 1191288 SEG343 5510 1191368 SEG26324701191 49 DB7 -3006 -1168129 C116972 -1168209 COM1268550 1098289 SEG342 5472 1098369 SEG26224321098 50 DB6 -2850 -1168130 C117073 -1168210 COM1288512 1191290 SEG341 5434 1191370 SEG26123941191 51 DB5 -2693 -1168131 C117173 -1168211 COM1308474 1098291 SEG340 5396 1098371 SEG26023561098 52 DB4 -2537 -1168132 C117273 -1168212 COM1328436 1191292 SEG339 5358 1191372 SEG25923181191 53 DB3 -2380 -1168133 VCIOUT 7453 -1168213 COM1348398 1098293 SEG338 5320 1098373 SEG25822801098 54 DB2 -2223 -1168134 VCIOUT 7553 -1168214 COM1368360 1191294 SEG337 5282 1191374 SEG25722421191 55 DB1/SDO -2067 -1168135 VCIOUT 7653 -1168215 COM1388322 1098295 SEG336 5244 1098375 SEG25622041098 56 DB0/SDI-1910 -1168136 VCIOUT 7753 -1168216 COM1408284 1191296 SEG335 5206 1191376 SEG25521661191 57 GNDDUM6 -1168137 -1754 VCI1 7933 -1168217 COM1428246 1098297 SEG334 5168 1098377 SEG25421281098 58 RW/RD*-1597 -1168138 VCI1 8033 -1168218 COM1448208 1191298 SEG333 5130 1191378 SEG25320901191 59 E/WR*/SCL -1168139 -1440 VCI1 8133 -1168219 COM1468170 1098299 SEG332 5092 1098379 SEG25220521098 60 GNDDUM7 -1168140 -1284 VCI1 8233 -1168220 COM1488132 1191300 SEG331 5054 1191380 SEG25120141191 61 RS -1127 -1168141 VCCDUM3 -1168221 8413 COM1508094 1098301 SEG330 5016 1098381 SEG25019761098 62 CS* -971 -1168142 VCCDUM4 -1168222 8513 COM1528056 1191302 SEG329 4978 1191382 SEG24919381191 63 VCC -791 -1168143 RESET3*8693 -1168223 COM1548018 1098303 SEG328 4940 1098383 SEG24819001098 64 VCC -690 -1168144 DUMMY10 -1168224 8850 COM1567980 1191304 SEG327 4902 1191384 SEG24718621191 65 VCC -590 -1168145 DUMMY11 -1168225 9193 COM1587942 1098305 SEG326 4864 1098385 SEG24618241098 66 VCC -490 -1168146 COM2 9201-981 226 COM1607904 1191306 SEG325 4826 1191386 SEG24517861191 67 AVCC -390 -1168147 COM4 9108-943 227 COM1627866 1098307 SEG324 4788 1098387 SEG24417481098 68 AVCC -290 -1168148 COM6 9201-905 228 COM1647828 1191308 SEG323 4750 1191388 SEG24317101191 69 AVCC -190 -1168149 COM8 9108-867 229 COM1667790 1098309 SEG322 4712 1098389 SEG24216721098 70 AVCC -90-1168150 COM10 9201-829 230 COM1687752 1191310 SEG321 4674 1191390 SEG24116341191 71 AGND 90-1168151 COM12 9108-791 231 COM1707714 1098311 SEG320 4636 1098391 SEG24015961098 72 AGND 190-1168152 COM14 9201-753 232 COM1727676 1191312 SEG319 4598 1191392 SEG23915581191 73 GND 290-1168153 COM16 9108-715 233 COM1747638 1098313 SEG318 4560 1098393 SEG23815201098 74 GND 390-1168154 COM18 9201-677 234 COM1767600 1191314 SEG317 4522 1191394 SEG23714821191 75 GND 490-1168155 COM20 9108-639 235 SEG396 7524 1098315 SEG316 4484 1098395 SEG23614441098 76 GND 590-1168156 COM22 9201-601 236 SEG395 7486 1191316 SEG315 4446 1191396 SEG23514061191 77 AGND 690-1168157 COM24 9108-563 237 SEG394 7448 1098317 SEG314 4408 1098397 SEG23413681098 78 AGND 791-1168158 COM26 9201-525 238 SEG393 7410 1191318 SEG313 4370 1191398 SEG23313301191 79 RESET2* 971-1168159 COM28 9108-487 239 SEG392 7372 1098319 SEG312 4332 1098399 SEG23212921098 80 OSC2 1127 -1168160 COM30 9201-449 240 SEG391 7334 1191320 SEG311 4294 1191400 SEG23112541191
7
HD66766R
Rev. 1.0-1 / September 2002
Table 3 cont. HD66766R PAD Coordinate (Laced* No.2) ( j No. pad nameX Y No. pad nameX Y No.pad name Y No.pad name Y Alignment X Y X X mark 401 SEG230 12161098481 SEG150 -18621098561 SEG70 -4902 1098641 COM1557980 1191 Cross -9000 -1121 402 SEG229 11781191482 SEG149 -19001191562 SEG69 -4940 1191642 COM1538018 1098 9000 -1121 403 SEG228 11401098483 SEG148 -19381098563 SEG68 -4978 1098643 COM1518056 Circle(Positive) 1191 -90941145 404 SEG227 11021191484 SEG147 -19761191564 SEG67 -5016 1191644 COM1498094 Circle(Negative) 1098 90941145 405 SEG226 10641098485 SEG146 -20141098565 SEG66 -5054 1098645 COM1478132 1191 L (Positive) -90041145 406 SEG225 10261191486 SEG145 -20521191566 SEG65 -5092 1191646 COM1458170 1098 L (Negative) 90041145 407 SEG224 988 1098487 SEG144 -20901098567 SEG64 -5130 1098647 COM1438208 1191 408 SEG223 950 1191488 SEG143 -21281191568 SEG63 -5168 1191648 COM1418246 1098 409 SEG222 912 1098489 SEG142 -21661098569 SEG62 -5206 1098649 COM1398284 1191 410 SEG221 874 1191490 SEG141 -22041191570 SEG61 -5244 1191650 COM1378322 1098 411 SEG220 836 1098491 SEG140 -22421098571 SEG60 -5282 1098651 COM1358360 1191 412 SEG219 798 1191492 SEG139 -22801191572 SEG59 -5320 1191652 COM1338398 1098 413 SEG218 760 1098493 SEG138 -23181098573 SEG58 -5358 1098653 COM1318436 1191 414 SEG217 722 1191494 SEG137 -23561191574 SEG57 -5396 1191654 COM1298474 1098 415 SEG216 684 1098495 SEG136 -23941098575 SEG56 -5434 1098655 COM1278512 1191 416 SEG215 646 1191496 SEG135 -24321191576 SEG55 -5472 1191656 COM1258550 1098 417 SEG214 608 1098497 SEG134 -24701098577 SEG54 -5510 1098657 COM1238588 1191 418 SEG213 570 1191498 SEG133 -25081191578 SEG53 -5548 1191658 COM1218626 1098 419 SEG212 532 1098499 SEG132 -25461098579 SEG52 -5586 1098659 COM1198664 1191 420 SEG211 494 1191500 SEG131 -25841191580 SEG51 -5624 1191660 COM1178702 1098 421 SEG210 456 1098501 SEG130 -26221098581 SEG50 -5662 1098661 COM1158740 1191 422 SEG209 418 1191502 SEG129 -26601191582 SEG49 -5700 1191662 COM1138778 1098 423 SEG208 380 1098503 SEG128 -26981098583 SEG48 -5738 1098663 COM1118816 1191 424 SEG207 342 1191504 SEG127 -27361191584 SEG47 -5776 1191664 COM1098854 1098 425 SEG206 304 1098505 SEG126 -27741098585 SEG46 -5814 1098665 COM1078892 1191 426 SEG205 266 1191506 SEG125 -28121191586 SEG45 -5852 1191666 DUMMY13 1183 -9193 427 SEG204 228 1098507 SEG124 -28501098587 SEG44 -5890 1098667 COM1059201995 428 SEG203 190 1191508 SEG123 -28881191588 SEG43 -5928 1191668 COM1039108957 429 SEG202 152 1098509 SEG122 -29261098589 SEG42 -5966 1098669 COM1019201919 430 SEG201 114 1191510 SEG121 -29641191590 SEG41 -6004 1191670 COM99-9108881 431 SEG200 76 1098511 SEG120 -30021098591 SEG40 -6042 1098671 COM97-9201843 432 SEG199 38 1191512 SEG119 -30401191592 SEG39 -6080 1191672 COM95-9108805 433 SEG198 -38 1098513 SEG118 -30781098593 SEG38 -6118 1098673 COM93-9201767 434 SEG197 -76 1191514 SEG117 -31161191594 SEG37 -6156 1191674 COM91-9108729 435 SEG196 -1141098515 SEG116 -31541098595 SEG36 -6194 1098675 COM89-9201691 436 SEG195 -1521191516 SEG115 -31921191596 SEG35 -6232 1191676 COM87-9108653 437 SEG194 -1901098517 SEG114 -32301098597 SEG34 -6270 1098677 COM85-9201615 438 SEG193 -2281191518 SEG113 -32681191598 SEG33 -6308 1191678 COM83-9108577 439 SEG192 -2661098519 SEG112 -33061098599 SEG32 -6346 1098679 COM81-9201539 440 SEG191 -3041191520 SEG111 -33441191600 SEG31 -6384 1191680 COM79-9108501 441 SEG190 -3421098521 SEG110 -33821098601 SEG30 -6422 1098681 COM77-9201463 442 SEG189 -3801191522 SEG109 -34201191602 SEG29 -6460 1191682 COM75-9108425 443 SEG188 -4181098523 SEG108 -34581098603 SEG28 -6498 1098683 COM73-9201387 444 SEG187 -4561191524 SEG107 -34961191604 SEG27 -6536 1191684 COM71-9108349 445 SEG186 -4941098525 SEG106 -35341098605 SEG26 -6574 1098685 COM69-9201311 446 SEG185 -5321191526 SEG105 -35721191606 SEG25 -6612 1191686 COM67-9108273 447 SEG184 -5701098527 SEG104 -36101098607 SEG24 -6650 1098687 COM65-9201235 448 SEG183 -6081191528 SEG103 -36481191608 SEG23 -6688 1191688 COM63-9108197 449 SEG182 -6461098529 SEG102 -36861098609 SEG22 -6726 1098689 COM61-9201159 450 SEG181 -6841191530 SEG101 -37241191610 SEG21 -6764 1191690 COM59-9108121 451 SEG180 -7221098531 SEG100 -37621098611 SEG20 -6802 1098691 COM57-9201 83 452 SEG179 -7601191532 SEG99 -38001191612 SEG19 -6840 1191692 COM55-9108 45 453 SEG178 -7981098533 SEG98 -38381098613 SEG18 -6878 1098693 COM53-9201 7 454 SEG177 -8361191534 SEG97 -38761191614 SEG17 -6916 1191694 COM51-9108-31 455 SEG176 -8741098535 SEG96 -39141098615 SEG16 -6954 1098695 COM49-9201-69 456 SEG175 -9121191536 SEG95 -39521191616 SEG15 -6992 1191696 COM47-9108 -107 457 SEG174 -9501098537 SEG94 -39901098617 SEG14 -7030 1098697 COM45-9201 -145 458 SEG173 -9881191538 SEG93 -40281191618 SEG13 -7068 1191698 COM43-9108 -183 459 SEG172 -10261098539 SEG92 -40661098619 SEG12 -7106 1098699 COM41-9201 -221 460 SEG171 -10641191540 SEG91 -41041191620 SEG11 -7144 1191700 COM39-9108 -259 461 SEG170 -11021098541 SEG90 -41421098621 SEG10 -7182 1098701 COM37-9201 -297 462 SEG169 -11401191542 SEG89 -41801191622 SEG9 -7220 1191702 COM35-9108 -335 463 SEG168 -11781098543 SEG88 -42181098623 SEG8 -7258 1098703 COM33-9201 -373 464 SEG167 -12161191544 SEG87 -42561191624 SEG7 -7296 1191704 COM31-9108 -411 465 SEG166 -12541098545 SEG86 -42941098625 SEG6 -7334 1098705 COM29-9201 -449 466 SEG165 -12921191546 SEG85 -43321191626 SEG5 -7372 1191706 COM27-9108 -487 467 SEG164 -13301098547 SEG84 -43701098627 SEG4 -7410 1098707 COM25-9201 -525 468 SEG163 -13681191548 SEG83 -44081191628 SEG3 -7448 1191708 COM23-9108 -563 469 SEG162 -14061098549 SEG82 -44461098629 SEG2 -7486 1098709 COM21-9201 -601 470 SEG161 -14441191550 SEG81 -44841191630 SEG1 -7524 1191710 COM19-9108 -639 471 SEG160 -14821098551 SEG80 -45221098631 COM1757600 1191711 COM17-9201 -677 472 SEG159 -15201191552 SEG79 -45601191632 COM1737638 1098712 COM15-9108 -715 473 SEG158 -15581098553 SEG78 -45981098633 COM1717676 1191713 COM13-9201 -753 474 SEG157 -15961191554 SEG77 -46361191634 COM1697714 1098714 COM11-9108 -791 475 SEG156 -16341098555 SEG76 -46741098635 COM1677752 1191715 COM9 -9201 -829 476 SEG155 -16721191556 SEG75 -47121191636 COM1657790 1098716 COM7 -9108 -867 477 SEG154 -17101098557 SEG74 -47501098637 COM1637828 1191717 COM5 -9201 -905 478 SEG153 -17481191558 SEG73 -47881191638 COM1617866 1098718 COM3 -9108 -943 479 SEG152 -17861098559 SEG72 -48261098639 COM1597904 1191719 COM1 -9201 -981 480 SEG151 -18241191560 SEG71 -48641191640 COM1577942 1098
8
HD66766R
HD66766R Block Diagram Description
Vcc AVcc
Rev. 1.0-1 / September 2002
Index Register (IR)
Control Register (CR)
IM2-1, IM0/ID CS* RS E/WR*/SCL RW/RD * DB0/SDI, DB1/SDO, to DB15 16
7
16
Address Counter ( AC ) Palette Register (RK, GK, BK) PWM Grayscale Circuit Bit Operation 16 12 16 Grayscale selector circuit VSL GND
System Interface - 16 bit - 8 bit - Clock synchoronized - serial
16
Segment drivers
Latch Circuit
Latch Circuit
Read data latch 16
Write data 64 latch 48
SEG1 to SEG396
RESET * TEST1 TEST2
16
Graphic RAM (GRAM) 46,464 bytes
OSC1
CPG
OSC2
Timinig generator
Scan data
generator circuit
LCD drive power supply circuit
Common driver
COM1 to COM176
C11+ to C12+
Vci1 VciOUT
C11- to C12-
BIASC VOUT
Vci2
C21+ to C24+
Figure 3 HD66766R Block Diagram Description
C21- to C24-
CE+
CE-
VREFL
VREFM
VSH
VCH
VM
VCL
9
HD66766R
Pin Functions
Table 4
Signals IM2-1, IM0/ID
Rev. 1.0-1 / September 2002
Pin Functional Description
Number of Pins 3 I/O I Connected to GND or VCC Functions Selects the MPU interface mode:
IM2 GND GND GND GND Vcc IM1 GND GND Vcc Vcc GND IM0/ID0 GND Vcc GND Vcc ID MPU Interface mode 68 system 16-bit bus interface 68 system 8-bit bus interface
80 system 16-bit bus interface 80 system 8-bit bus interface
Clock synchronized serial interface
When a serial interface is selected, the IM0 pin is used as the ID setting for a device code. CS* 1 I MPU Selects the HD66766R: Low: HD66766R is selected and can be accessed High: HD66766R is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register. Low: Index/status High: Control
RS
1
I
MPU
For a register or a synchronous clock interface, fixed to the Vcc or GND level. E/WR*/SCL 1 I MPU For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 80-system bus interface, serves as a write strobe signal and writes data at the low level. For a synchronous clock interface, serves as the synchronous clock signal. RW/RD* 1 I MPU For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read For an 80-system bus interface, serves as a read strobe signal and reads data at the low level. For a synchronous clock interface, fixed to the Vcc or GND level. DB0/SDI 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as the serial data input pin (SDI). The input level is read on the rising edge of the SCL signal. DB1/SDO 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as a serial data output pin (SDO). Successive bit values are output on the falling edge of the SCL signal.
10
HD66766R
Table 4 cont.
Signals DB2-DB15 Number of Pins 14 I/O I/O Connected to MPU Functions
Rev. 1.0-1 / September 2002
SEG1- SEG396
396
O
COM1- COM176
176
O
VCH, VCL
2
--
VM
1
--
VSH
1
--
VciOUT
1
--
Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a synchronous clock interface or unused pins, fixed to the Vcc or GND level. LCD Output signals for segment drive. In the display-off period (D1-0 = 00, 01) or standby mode (STB = 1), all pins output GND level. The SGS bit can change the shift direction of the segment signal. For example, if SGS = 0, RAM address 0000 is output from SEG1. If SGS = 1, it is output from SEG396. SEG1, SEG4, SEG7, ... display red (R), SEG2, SEG5, SEG8, ... display green (G), and SEG3, SEG6, SEG9, ... display blue (B) (SGS = 0). LCD Output signals for common drive. In the display-off period (D1-0 = 00, 01) sleep mode (SLP = 1) or standby mode (STB = 1), all pins output GND level. The CMS bit can change the shift direction of the common signal. For example, if CMS = 0, driver outputs from COM1 to COM176. If CMS = 1, driver outputs COM176 to COM1. Note that start position of the common driver output is changed by screen diving position function. Capacitor for Selection level for the common signal. When internal power stabilization, supply is used, connect the capacitors for stabilization to shot key barrier VCH AND VCL, and shot key barrier diode to VCL. diode or external When internal power supply is not used, supply external power supply voltage. Capacitor for Non-selection level for the common signal. When internal stabilization or operational amplifier is used, it is output of the internal external power operational amplifier and connect the capacitors for supply stabilization. When internal operational amplifier is not used, supply external voltage. Capacitor for Selection level for the segment signal. When internal stabilization or operational amplifier is used, it is output of the internal external power operational amplifier and connect the capacitors for supply stabilization. When internal operational amplifier is not used, supply external voltage. Vci1 and Outputs a regulated voltage derived from Vcc. Connect a capacitor for stabilization. When this pin is not used, capacitor for stabilization or leave it open. open VciOUT or power supply Capacitor for stabilization or open Step-up capacitance Step-up capacitance Voltage-input pin for step-up circuit 1. When the Vci adjuster is used, input the power supply from VciOUT. When not used, input the external power supply. Connect capacitor for stabilization. When the internal power supply circuit is not used, leave this pin open. A voltage that doubles or triples the voltage between Vci1 and GND is output here. The step-up factor can be set in an internal register. When step-up circuit is used, connect a step-up capacitor.
Vci1
1
--
Vci2
1
--
VOUT
1
--
C11+, C11-
2
--
11
HD66766R
Table 4 cont.
Signals C12+, C12C21+, C21C22+, C22C23+, C23C24+, C24CEP, CEM 2 2 2 2 2 2 Number of Pins I/O -- -- -- -- -- -- Connected to Step-up capacitance Step-up capacitance Step-up capacitance Step-up capacitance Step-up capacitance Step-up capacitance or open VCC or external power supply Functions
Rev. 1.0-1 / September 2002
When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. When step-up circuit is used, connect a step-up capacitor. Connect a step-up capacitor to generate VCL level by VCH and VM. When step-up circuit is not used, leave this pin open. Inputs reference voltage for LCD drives power supply. Input lower level than Vcc. Since input current does not run, level input, which is divided by resistors, is also possible. Connect capacitor for stabilization for internal power supply. When internal operational amplifier is not used, supply external voltage. Connect capacitor for stabilization for internal power supply. VCC: + 2.2 V to + 3.6 V; GND (logic): 0 V VCC for power supply circuit. Input the same level of voltage as VCC.
VREFL
1
--
VREFM
1
--
Capacitor for stabilization or external power supply Capacitor for stabilization or open Power supply -- --
BIASC
1
--
VCC, GND AVCC AGND OSC1, OSC2 RESET*
2 1 1 2
-- -- -- I/O
GND for power supply circuit.
Oscillation-resistor Connect an external resistor for R-C oscillation. When providing clocks from outside, input clock to OCS1 and leave OSC2 open. MPU or external R-C circuit Open unused pins Input pins Input pins -- GND Reset pin. Initializes the LSI when low. Must be reset after power-on. Since HCD66766RBP has three RESET pins, use one pin and open unused two pins. Outputs the internal VCC level; shorting this pin sets the adjacent input pin to the VCC level. Outputs the internal GND level; shorting this pin sets the adjacent input pin to the GND level. Dummy pad. Must be left disconnected. Test pin. Must be fixed at GND level.
1
I
VccDUM GNDDUM Dummy TEST1, TEST 2
1 1 1 2
O O -- I
12
HD66766R
Block Function Description
System Interface
Rev. 1.0-1 / September 2002
The HD66766R has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16bit/8-bit bus, and a Clock synchronized serial interface. The IM2-0 pins select the interface mode. The HD66766R has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written into the WDR and then is automatically written into the GRAM by internal operation. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are normal. Execution time for instruction excluding oscillation start is 0-clock cycle and instructions can be written in succession. Table 5 Register Selection (8/16 Parallel Interface)
68-series Bus R/W 0 1 0 1 RS 0 0 1 1 Operations Writes indexes into IR Reads internal status Writes into control registers and GRAM through WDR Reads from GRAM through RDR
80-series Bus WR 0 1 0 1 RD 1 0 1 0
Table 6
Start bytes R/W Bit 0 1 0 1
Register Selection (Clock synchronized Serial Interface)
RS Bit 0 0 1 1 Operations Writes indexes into IR Reads internal status Writes into control registers and GRAM through WDR Reads from GRAM through RDR
Bit Operation The HD66766R supports the following functions. A write data mask function that selects data into the GRAM in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With the 16-bit bus interface, these functions can greatly reduce the processing lord of the MPU graphics software the display data in the GRAM at high speed. For details, see the Graphics Operation Function section. Address Counter (AC) The address counter (AC) assigns address to the GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically incremented by 1 (or decrement by 1). After reading from the GRAM, the AC is not updated.
13
HD66766R
Graphics RAM (GRAM)
Rev. 1.0-1 / September 2002
The graphics RAM (GRAM) has twelve bits/pixel and stores the bit-pattern data of 132 x 176 bytes. PWM Grayscale Palette Circuit The grayscale palette generates a PWM signal, which corresponds to specified grayscale level. Any 65K out of the 140K possible colors can be displayed at the same time. Grayscale Control Circuit The grayscale control circuit performs 16-grayscale control with the pulse width modulation (PWM) method for grayscale display for each color. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The RAM read timing for display and internal operation timing by MPU access is generated separately to avoid interference with one another. Oscillation Circuit (OSC) The HD66766R can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 176 common signal drivers (COM1 to COM176) and 396 segment signal drivers (SEG1 to SEG396). Display pattern data from GRAM is latched to the 396-bit latch circuit. The latched data then enables the segment signal drivers to generate drive waveform outputs. The common driver outputs one of the VCH, VM or VCL voltage level. The SGS bit can change the shift direction of 396-bit data for the segment. The CMS bit can also change the shift direction for the common by selecting an appropriate direction for the device-mounting configuration. When display is off, or during the standby or sleep mode, all the above common and segment signal drivers output the GND level, halting the display. LCD drive power supply circuit LCD drive power supply circuit generates VCH, VSH, VM and VCL voltage level to drive LCD panel.
14
HD66766R
GRAM ADDRESS DIAGRAM (HD66766R)
Rev. 1.0-1 / September 2002
Table 7 Relationship between GRAM address and display position (SGS = "0")
S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396
DB 0
S10
DB 15
S1
S2
S3
S4
S5
S6
S7
S8
CMS=0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20
CMS=1 COM176 COM175 COM174 COM173 COM172 COM171 COM170 COM169 COM168 COM167 COM166 COM165 COM164 COM163 COM162 COM161 COM160 COM159 COM158 COM157
DB 15
DB 0
DB 15
DB 0
DB 15
S9
SEG/COM pins
DB 0
DB 0
S12
S11
DB 15
DB DB 0 15
DB DB 0 15
DB DB 0 15
"0000"H "0100"H "0200"H "0300"H "0400"H "0500"H "0600"H "0700"H "0800"H "0900"H "0A00"H "0B00"H
"0001"H "0101"H "0201"H "0401"H "0501"H "0601"H "0701"H "0801"H "0901"H "0A01"H "0B01"H
"0002"H "0102"H "0202"H "0402"H "0502"H "0602"H "0702"H "0802"H "0902"H "0A02"H
"0003"H "0103"H "0203"H "0303"H "0403"H "0503"H "0603"H "0703"H "0803"H "0903"H "0A03"H
"0080"H "0180"H "0280"H "0380"H "0480"H "0580"H "0680"H "0780"H "0880"H "0980"H "0A80"H "0B80"H "0C80"H "0D80"H "0E80"H "0F80"H "1080"H "1180"H "1280"H "1380"H
"0081"H "0181"H "0281"H "0381"H "0481"H "0581"H "0681"H "0781"H "0881"H "0981"H "0A81"H "0B81"H "0C81"H "0D81"H "0E81"H "0F81"H "1081"H "1181"H "1281"H "1381"H
"0082"H "0182"H "0282"H "0382"H "0482"H "0582"H "0682"H "0782"H "0882"H "0982"H
"0083"H "0183"H "0283"H "0383"H "0483"H "0583"H "0683"H "0783"H "0883"H "0983"H
"0301"H "0302"H
"0A82"H "0A83"H "0B82"H "0B83"H "0C82"H "0C83"H "0D82"H "0D83"H "0E82"H "0E83"H "0F82"H "0F83"H "1082"H "1083"H "1182"H "1282"H "1382"H "1183"H "1283"H "1383"H
"0B02"H "0B03"H "0C00"H "0C01"H "0C02"H "0C03"H "0D00"H "0D01"H "0D02"H "0D03"H "0E00"H "0E01"H "0E02"H "0E03"H "0F00"H "1000"H "1100"H "1200"H "1300"H "0F01"H "1001"H "1101"H "1201"H "1301"H "0F02"H "1002"H "1102"H "1202"H "1302"H "0F03"H "1003"H "1103"H "1203"H "1303"H
COM169 COM170 COM171 COM172 COM173 COM174 COM175 COM176
COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
"A800"H "A900"H
"A801"H "A901"H
"A802"H "A803"H "A902"H "A903"H "AA02"H "AA03"H "AB02"H "AB03"H
"A880"H "A980"H "AA80"H "AB80"H
"A881"H "A981"H "AA81"H "AB81"H
"A882"H "A883"H "A982"H "A983"H "AA82"H "AA83"H "AB82"H "AB83"H "AC82"H "AC83"H "AD82"H "AD83"H "AE82"H "AE83"H "AF82"H "AF83"H
"AA00"H "AA01"H "AB00"H "AB01"H
"AC00"H "AC01"H "AC02"H "AC03"H "AD00"H "AD01"H "AD02"H "AD03"H "AE00"H "AE01"H "AF00"H "AF01"H "AE02"H "AE03"H "AF02"H "AF03"H
"AC80"H "AC81"H "AD80"H "AD81"H "AE80"H "AE81"H "AF80"H "AF81"H
Table 8 Relationship between GRAM data and output pin GRAM DATA Selected palette Output pin
DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
PK palette SEG (3n+1)
PK palette + FRC
PK palette
SEG (3n+2) SEG (3n+3) Note: n = Lower 8 bits address (0 to 131)
15
HD66766R
Table 9
Rev. 1.0-1 / September 2002
Relationship between GRAM address and display position (SGS = "1")
S385 S386 S387 S388 S389 S390 S391 S392 S393 S394
DB 0
S395
S1 S2
S3 S4
S5 S6
S7
CMS=0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
CMS=1
DB 0
DB 15
DB 0
DB 15
DB 0
S8 S9
SEG/COM pins
DB 15
DB 0
DB 15
DB 0
DB 15
DB 0
DB 15
DB 0
DB 15
DB 15
COM176 "0083"H "0082"H COM175 "0183"H "0182"H COM174 "0283"H "0282"H COM173 "0383"H "0382"H COM172 "0483"H "0482"H COM171 "0583"H "0582"H COM170 "0683"H "0682"H COM169 "0783"H "0782"H COM168 "0883"H "0882"H
"0081"H "0080"H "0181"H "0180"H "0281"H "0280"H "0381"H "0380"H "0481"H "0480"H "0581"H "0580"H "0681"H "0680"H "0781"H "0780"H "0881"H "0880"H "0981"H "0980"H
"0003"H "0002"H "0103"H "0102"H "0203"H "0202"H "0303"H "0302"H "0403"H "0402"H "0503"H "0502"H "0603"H "0602"H "0703"H "0702"H "08030"H "0802"H "0903"H "0902"H
"0001"H "0000"H "0101"H "0100"H "0201"H "0200"H "0301"H "0300"H "0401"H "0400"H "0501"H "0500"H "0601"H "0600"H "0701"H "0700"H "0801"H "0800"H "0901"H "0900"H
COM10 COM167 "0983"H "0982"H COM11 COM166 "0A83"H "0A82"H "0A81"H "0A80"H COM12 COM165 "0B83"H "0B82"H "0B81"H "0B80"H COM13 COM164 "0C83"H "0C82"H "0C81"H "0C80"H COM14 COM163 "0D83"H "0D82"H "0D81"H "0D80"H COM15 COM162 "0E83"H "0E82"H "0E81"H "0E80"H COM16 COM161 "0F83"H "0F82"H "0F81"H "0F80"H COM17 COM160 "1083"H "1082"H COM18 COM159 "1183"H "1182"H COM19 COM158 "1283"H "1282"H COM20 COM157 "1383"H "1382"H "1081"H "1080"H "1181"H "1180"H "1281"H "1280"H "1381"H "1380"H
"0A03"H "0A02"H "0A01"H "0A00"H "0B03"H "0B02"H "0B01"H "0B00"H "0C03"H "0C02"H "0C01"H "0C00"H "0D03"H "0D02"H "0D01"H "0D00"H "0E03"H "0E02"H "0E01"H "0E00"H "0F03"H "0F02"H "0F01"H "0F00"H "1003"H "1002"H "1001"H "1000"H "1103"H "1102"H "1101"H "1100"H "1203"H "1202"H "1201"H "1200"H "1303"H "1302"H "1301"H "1300"H
COM169 COM170 COM171 COM172 COM173 COM174 COM175 COM176
COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
"A883"H "A882"H "A881"H "A880"H "A983"H "A982"H "A981"H "A980"H "AA83"H "AA82"H "AA81"H "AA80"H "AB83"H "AB82"H "AB81"H "AB80"H "AC83"H "AC82"H "AC81"H "AC80"H "AD83"H "AD82"H "AD81"H "AD80"H "AE83"H "AE82"H "AE81"H "AE80"H "AF83"H "AF82"H "AF81"H "AF80"H
"A803"H "A802"H "A801"H "A800"H "A903"H "A902"H "A901"H "A900"H "AA03"H "AA02"H "AA01"H "AA00"H "AB03"H "AB02"H "AB01"H "AB00"H "AC03"H "AC02"H "AC01"H "AC00"H "AD03"H "AD02"H "AD01"H "AD00"H "AE03"H "AE02"H "AE01"H "AE00"H "AF03"H "AF02"H "AF01"H "AF00"H
Table 10 GRAM DATA Selected palette Output pin
Relationship between GRAM data and output pin
DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
PK palette SEG (396-3n)
PK palette + FRC
PK palette
SEG (395-3n) SEG (394-3n) Note: n = Lower 8 bits address (0 to 131)
16
S396
S10 S11 S12
HD66766R
Instructions Outline
Rev. 1.0-1 / September 2002
The HD66766R uses the 16-bit bus architecture. Before the internal operation of the HD66766R starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the HD66766R is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66766R instructions. * There are eight categories of instructions that: * Specify the index * * Read the status Control the display
* Control power management * Process the graphics data * Set internal GRAM addresses * Transfer data to and from the internal GRAM * Set grayscale level for the internal grayscale palette table Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. Because instructions are executed in 0 cycles, they can be written in succession.
17
HD66766R
Instruction Descriptions Index: IR
Rev. 1.0-1 / September 2002
The index instruction specifies the RAM control indexes (R00h to R3Fh). It sets the register number in the range of 000000 to 111001 in binary form. However, R40 to R44 are disabled since they are test registers.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
0
*
*
*
*
*
*
*
*
*
ID6 ID5
ID4 ID3 ID2 ID1 ID0
Figure 4 Status Read: SR
Index Instruction
The status read instruction reads the internal status of the HD66766R. L7-0: Indicate the driving raster-row position where the liquid crystal display is being driven. C6-0: Read the contrast setting values (CT6-0)
R/W
RS
DB15 DB14
DB13 DB12
DB11 DB10
DB9 DB8
DB7 DB6 DB5
DB4 DB3
DB2
DB1
DB0
R
0
L7
L6
L5
L4
L3
L2
L1
L0
0
C6
C5 C4
C3
C2
C1
C0
Figure 5 Start Oscillation (R00h)
Status Read Instruction
The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register is read forcibly, "0766"H is read.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
w R
1 1
*
0
*
0
*
0
*
0
*
0
*
1
*
1
*
1
*
0
*
1
*
1
*
0
*
0
*
1
*
1
1 0
Figure 6
Start Oscillation Instruction
18
HD66766R
Driver Output Control (R01h)
Rev. 1.0-1 / September 2002
R/W
RS
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
w
1
0
0
0
0
0
0
CMS SGS
0
0
0
NL4
NL3 NL2
NL1 NL0
Figure 7
Driver Output Control Instruction
CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1 shifts to COM176. When CMS = 1, COM176 shifts to COM1. SGS: Selects the output shift direction of the segment driver. When SGS = 0, data are output SEG1 to SEG396. When SGS = 1, data are output SEG396 to SEG1. When SGS = 0, SEG1 pin assigns the color display to . When SGS = 1, SEG396 pin assigns . Re-write to the RAM when intending to change the SGS bit. NL4-0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows. GRAM address mapping does not depend on the setting value of the drive duty ratio.
19
HD66766R
Table 11 NL Bits and Drive Duty
Rev. 1.0-1 / September 2002
NL4 NL3 NL2 NL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
NL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display Size 396 x 8 dots 396 x 16 dots 396 x 24 dots 396 x 32 dots 396 x 40 dots 396 x 48 dots 396 x 56 dots 396 x 64 dots 396 x 72 dots 396 x 80 dots 396 x 88 dots 396 x 96 dots 396 x 104 dots 396 x 112 dots 396 x 120 dots 396 x 128 dots 396 x 136 dots 396 x 144 dots 396 x 152 dots 396 x 160 dots 396 x 168 dots 396 x 176 dots
LCD drive duty cycle 1/8 Duty 1/16 Duty 1/24 Duty 1/32 Duty 1/40 Duty 1/48 Duty 1/56 Duty 1/64 Duty 1/72 Duty 1/80 Duty 1/88 Duty 1/96 Duty 1/104 Duty 1/112 Duty 1/120 Duty 1/128 Duty 1/136 Duty 1/144 Duty 1/152 Duty 1/160 Duty 1/168 Duty 1/176 Duty
Common driver used CMS="0" Com1 - Com8 Com1 - Com16 Com1 - Com24 Com1 - Com32 Com1 - Com40 Com1 - Com48 Com1 - Com56 Com1 - Com64 Com1 - Com72 Com1 - Com80 Com1 - Com88 Com1 - Com96 Com1 - Com104 Com1 - Com112 Com1 - Com120 Com1 - Com128 Com1 - Com136 Com1 - Com144 Com1 - Com152 Com1 - Com160 Com1 - Com168 Com1 - Com176 CMS="1" Com176 - Com169 Com176 - Com161 Com176 - Com153 Com176 - Com145 Com176 - Com137 Com176 - Com129 Com176 - Com121 Com176 - Com113 Com176 - Com105 Com176 - Com97 Com176 - Com89 Com176 - Com81 Com176 - Com73 Com176 - Com65 Com176 - Com57 Com176 - Com49 Com176 - Com41 Com176 - Com33 Com176 - Com25 Com176 - Com17 Com176 - Com9 Com176 - Com1
20
HD66766R
LCD-Driving-Waveform Control (R02h)
Rev. 1.0-1 / September 2002
R/W
RS
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
0
RST B/C
EOR
0
0
NW5 NW4 NW3 NW2 NW1 NW0
Figure 8 LCD-Driving-Waveform Control Instruction B/C: When B/C = 0, a B-pattern waveform is generated and alternates in every frame for LCD drive. When B/C = 1, a C-pattern waveform is generated and alternates in each raster-row specified by bits EOR and NW4-NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row Reversed AC Drive section. EOR: When the C-pattern waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals and the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the number of the LCD drive duty ratio and the n raster-row. For details, see the n-raster-row Reversed AC Drive section. RST: When RST = 1, software reset function is started. This function is the same as hardware RESET pin. It takes 10 clock cycle period. This bit is automatically cleared after reset function is completed. Therefore, before 10-clock cycle other instruction can not be issued. Do not set the RST bit during stand-by mode. NW5-0: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C = 1). NW5-NW0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected. Power Control 1 (R03h) Power Control 2 (R0Ch) R/W RS DB15DB14 DB13DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 w w 1 1 BS3 BS2 BS1 BS0 BT3 BT2 BT1 BT0 0 0 0 0 0 0 0 0 0 0 D C 2 D C 1 D C 0 A P 1 A P 2 S L P S TB 0 0 0 0 VC2 VC1 VC0
Figure 9 Power Control Instruction BS3-0: The LCD drive bias value is set. The LCD drive bias value can be selected according to its drive duty ratio and voltage. BT2-0: The output factor of step-up circuit is switched. The LCD drive voltage level can be selected according to its drive duty ratio and bias. Lower amplification of the step-up circuit consumes less current. BT3: Operation/halt of voltage inverting circuit is set. BT3="0": voltage-inverting circuit is halted. BT3="1": voltage-inverting circuit is operated. See the Power-on/off Sequence section to be activated.
21
HD66766R
Rev. 1.0-1 / September 2002
DC2-0: The operating frequency in the step-up circuit is selected. When the step-up operating frequency is high, the driving ability of the step-up circuit becomes high, but the current consumption is increased. Adjust the frequency considering the step-up ability and the current consumption. AP1-0: The amount of fixed current from the fixed current source in the operational amplifier for the LCD is adjusted. When the amount of fixed current is large, the LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when AP1-0 = "00", the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. VC2-0: Set an adjustment factor for the Vci1 voltage (VC2-0). SLP: When SLP = 1, the HD66766R enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. Power control (BS2-0, BT3-0, DC2-0, AP1-0, SLP, STB)
During the sleep mode, the other GRAM data and instructions cannot be updated although they are retained. STB: When STB = 1, the HD66766R enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. a. Standby mode cancel (STB = "0") b. Start oscillation During the standby mode, the GRAM data and instructions may be lost. To prevent this, they must be set again after the standby mode is canceled. The VSH voltage should be controlled to be less than supply voltage or device proof voltage level since VCH voltage level is generated by bias amplifier ratio corresponding to LCD driving bias value and boosting ratio of the step-up circuit 2.
22
HD66766R
Table 12 Display bias setting table
Rev. 1.0-1 / September 2002
Determine the LCD drive bias according to its display duty, and select combination of boosting ratio of the step-up circuit 2 and bias amplifier ratio so as not to exceed voltage control of Vci2 and VCH. See the LCD Voltage Generation Circuit regarding how to determine the LCD drive bias, VCH voltage and contrast adjustment for the following settings.
LCD driving bias 1/2
1/4
1/6
1/8
1/9
1/10
1/11
1/12
1/13
Booster ratio of the step-up circuit 2 (ND2) x2 x3 x4 x2 x3 x4 x2 x3 x4 x2 x3 x4 x2 x3 x4 x2 x3 x4 x2 x3 x4 x3 x4 x5 x3 x4 x5
BS3 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0
BS2 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1
BS1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 1 1
BS0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1
Bias ratio (NB) 0.75 N/A N/A 1.25 0.825 N/A 1.75 1.165 N/A N/A 1.50 1.125 N/A 1.675 1.25 N/A 1.825 1.375 N/A 2.00 1.50 N/A 1.625 1.3 N/A 1.75 1.4
Vci2 (Vci2VOU T-0.5V) 1.50 x VM 2.50 x VM 1.75 x VM 3.50 x VM 2.33 x VM 3.00 x VM 2.25 x VM 3.35 x VM 2.50 x VM 3.65 x VM 2.75 x VM 4.00 x VM 3.00 x VM 3.25 x VM 2.60 x VM 3.45 x VM 2.80 x VM
VCH (VCH22V) Vci2 x 2 Vci2 x 2 Vci2 x 3 Vci2 x 2 Vci2 x 3 Vci2 x 3 Vci2 x 4 Vci2 x 3 Vci2 x 4 Vci2 x 3 Vci2 x 4 Vci2 x 3 Vci2 x 4 Vci2 x 4 Vci2 x 5 Vci2 x 4 Vci2 x 5
23
HD66766R
Table 13 Display bias setting table
VC2 0 0 0 0 1 1 1 1 VC1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 0 1 0 1 Vci1 control range 0.92 x Vcc 0.87 x Vcc 0.83 x Vcc 0.8 x Vcc 0.76 x Vcc 0.73 x Vcc 0.68 x Vcc Vci1 control amplifier suspends. (Vci1 can be supplied externally.)
Rev. 1.0-1 / September 2002
Table 14 AP bits and amount of fixed current
AP1 0 0 1 1 AP0 0 1 0 1 Amount of fixed current in the operational amplifier Operational amplifier and booster do not operate. Small Middle Large
Table 15 Output voltage ratio of the booster 1 and 2
BT2 0 0 0 0 1 1 1 1 BT1 0 0 1 1 0 0 1 1 BT0 0 1 0 1 0 1 0 1 VOUT output of the booster 1 (Use VOUT within the range of 4.0 to 5.75V.)
2 x Vci1 3 x Vci1 2 x Vci1 3 x Vci1 2 x Vci1 3 x Vci1 2 x Vci1 3 x Vci1
VCH output of the booster 2 (Set VCH lower than 22.0V.)
2 x Vci2 2 x Vci2 3 x Vci2 3 x Vci2 4 x Vci2 4 x Vci2 5 x Vci2 5 x Vci2
Set the factor of the booster 2 according to voltage of Vci2 and VCH. When the factor is set low, current consumption can be lowered.
24
HD66766R
Table 16 Operating clock frequency of the Booster 1 and 2
DC2 0 0 0 0 1 1 1 1 DC1 0 0 1 1 0 0 1 1 DC0 0 1 0 1 0 1 0 1 Operating clock frequency in the booster 1 32-divided clock 64-divided clock 32-divided clock 64-divided clock 32-divided clock 64-divided clock 32-divided clock 64-divided clock
Rev. 1.0-1 / September 2002
Operating clock frequency in the voltage inverting circuit and the booster 2 32-divided clock 32-divided clock 64-divided clock 64-divided clock 96-divided clock 96-divided clock 128-divided clock 128-divided clock
Operation of voltage inverting circuit Table 17 BT3 0 1
VCL output of the voltage inverting circuit (Set VCL no lower than -22.0V.) Halt boosting Output voltage between VCH and VM by inverting
Set activation of voltage inverting circuit with output of the booster 2 stable. *See the Power-on/off Sequence section. DB 15 Contrast Control (R04h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
1
0
0
0
0
0
VR2 VR1 VR0
0
CT6 CT5 CT4 CT3 CT2 CT1 CT0
Figure 10 Contrast Control Instruction CT6-0: These bits control the LCD drive voltage to adjust 128-step contrast.
Table 18 Contrast control
CT6 0 0 0 0 0 : : 1 1 1 1 CT5 0 0 0 0 0 : CT4 0 0 0 0 0 : : 1 1 CT3 0 0 0 0 0 : : 1 1 CT2 0 0 0 0 1 : : 1 1 CT1 0 0 1 1 0 : : 1 1 CT0 0 1 0 1 0 : : 0 1 Contrast 1.016R (Minimum) 1.008R 1.000R 0.992R 0.984R : : 0.008R 0.000R (Maximum)
25
HD66766R
Rev. 1.0-1 / September 2002
VR2-0: These bits amplifies 1.1 to 3.4 times the VREFL as output voltage VREFM of LCD drive reference voltage generation circuit. The VREFM should be smaller than VOUT level. Table 19 Contrast control
VR2 0 0 0 0 1 1 1 VR1 0 0 1 1 0 0 1 VR0 0 1 0 1 0 1 0 VREFM voltage VREFL x 1.1 VREFL x 1.3 VREFL x 1.4 VREFL x 1.5 VREFL x 1.7 VREFL x 1.8 VREFL x 3.4
26
HD66766R
Entry Mode (R05h ) Compare resister (R06h)
Rev. 1.0-1 / September 2002
The write data sent from the microcomputer is modified in the HD66766R and written to the GRAM. The display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For detail, see the Graphics Operation Function section.
R/W
RS
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W W
1 1
SPR
0
0
0
0
0
HWM
0
0
0
I/D1 I/D0
AM LG2 LG1 LG0
CP15 CP14 CP13 CP12 CP11 CP10 CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
Figure 11 Compare Resister Instruction HWM: When HWM=1, data can be written to the GRAM at high speed. In high-speed write mode, four words of data are written to the GRAM in a single operation after the writing to RAM four times. Write to RAM four times, otherwise the four words cannot be written to the GRAM. Thus, set the lower 2 bits to 0 when setting the RAM address. For details, see the High-Speed RAM Write Mode section. I/D1-0: When I/D1-0 = "1", the address counter (AC) is automatically incremented by 1 after the data is written to the GRAM. When I/D1-0 = "0", the AC is automatically decremented by 1 after the data is written to the GRAM. The increment/decrement setting of the address counter by I/D1-0 is done independently for the upper (AD15-8) and lower (AD7-0) addresses. The AM bit sets the direction of moving through the addresses when the GRAM is written to. AM set the automatic update method of the AC after the data is written to the GRAM. When AM= "0", the data is continuously written in parallel. When AM = "1", the data is continuously written vertically. When window address range is specified, the GRAM in the window address range can be written to according to the I/D1-0 and AM settings. SPR: When SPR=1, 4096colors are displayed. 12 bit (DB11-DB0) are used for this display. Refer to "4096 color display function" in page 57 for details.
I/D1-0="00"
Horizontal: decrement Vertical: decrement
0000h
I/D1-0="01"
Horizontal: increment Vertical: decrement
0000h
I/D1-0="10"
Horizontal: decrement Vertical: increment
0000h
I/D1-0="11"
Horizontal: increment Vertical: increment
0000h
AM="0" Horizontal
AF83h 0000h 0000h AF83h 0000h AF83h 0000h AF83h
AM="1" Vertical
AF83h AF83h AF83h AF83h
Note: When a window address range has been set the GRAM can only be written to within that range.
Figure 12
Address Direction Settings
27
HD66766R
Rev. 1.0-1 / September 2002
LG2-0: Compare the data read from the GRAM by the microcomputer with the compare resisters (CP150) by a compare/logical operation and writes the results to GRAM. For details, see the Logical/Compare Operation Function. CP15-0: Set the compare resister for the compare operation with the data read from the GRAM or written by the microcomputer.
DB15 DB14 DB13 DB12 DB11 DB10 DB9 Write data sent from the microcomputer (DB15-0) DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
Logical/compare operation (LG2 - 0)
Logical operation (with compare resister) LG2-0 = "110": Replacement of matched write data LG2-0 = "111": Replacement of unmatched writes data
Write data mask * (WM15 - 0)
Write data mask (WM15-0)
GRAM
Note: The write data mask ( WM15-0 ) is set by the resister in the (20) RAM Write Data Mask section.
Figure 13 Logical/Compare Operation for the GRAM
28
HD66766R
Display Control (R07h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Rev. 1.0-1 / September 2002
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
0
VLE2 VLE1
SPT
0
0
0
0
B/W REV
D1
D0
Figure 14 Display Control VLE2-1: When VLE1 = 1, a vertical scroll is performed in the 1st screen. When VLE2 = "1", a vertical scroll is performed in the 2nd screen. Vertical scrolling on the two screens can be independently controlled. SPT: When SPT = 1, the 2-division LCD drive is performed. For details, see the Screen-division Driving Function section. B/W: When B/W = "1", displayed data can be "all" or "all off" regardless GRAM contents. (B/W = "1", REV = "0": all pixel on, B/W = "1", REV = "1": all pixel off) When B/W = "1", grayscale palette has to be default value. REV: Displays all character and graphics display sections with reversal when REV = 1. For details, see the Reversed Display Function section. Since the grayscale level can be reversed, display of the same data is enabled on normally-white and normally-black panels. D1-0: Display is on when D1 = "1" and off when D1 = 0. When off, the display data remains in the GRAM, and can be displayed instantly by setting D1 = "1". When D1 is "0", the display is off with all of the SEG/COM pin outputs set to the GND level. Because of this, the HD66766R can control the charging current for the LCD with AC driving. When D1-0 = "01", the internal display of the HD66766R is performed although the display is off. When D1-0 = "00", the internal display operation halts and the display is off. Table 20 D Bits and Operation
D1 0 0 1 1 D0 0 1 0 1 SEG/COM Output GND GND Unlit display Display HD66766R Internal Display Operation Halt Operate Operate Operate
Notes: 1. Writing from the microcomputer to the GRAM is independent from the state of D1-0. 2. In the sleep and standby modes, D1-0 = 00. However, the register contents of D1-0 are not modified.
29
HD66766R
Frame Cycle Control (R0Bh)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
Rev. 1.0-1 / September 2002
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
0
0
DIV1 DIV0
0
0
0
0 RTN3 RTN2 RTN1 RTN0
Figure 15 RTN3-0: Set the line retrace period (RTN3-0) to be added to raster-row cycles. becomes long according to the number of clocks set at RTN3-0. The raster-row cycle
DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by clocks which are frequency divided according to the DIV1-0 setting. Frame frequency can be adjusted along with the line retrace period (RTN3-0). When changing the drive-duty, adjust the frame frequency. For details, see the Frame Frequency Adjustment Function section. Table 21 RTN Bits and Clock Cycles
RTN3 RTN2 RTN1 RTN1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 1 1 : 1 1 0 1 0 1 : 0 1
Line retrace period (Clock Cycles) Clock Cycles per one raster-row
0 clock 1 clock 2 clock 3 clock : 14 clock 15 clock
26 clock 27 clock 28 clock 29 clock : 40 clock 41 clock
Table 22 DIV Bits and Clock Frequency
DIV1 0 0 1 1 DIV0 0 1 0 1 Division ratio 1 2 4 8 Internal Operation Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8
* fosc=R-C oscillation frequency
Formula for the frame frequency
Frame frequency = fosc Clock cycles per raster-row xdivision ratio x 1/duty cycle fosc: RC oscillation frequency Duty: Drive duty (NL bit) Division ratio: DI V bit Clock cycles per raster-row: (RTN+26) clock [Hz]
30
HD66766R
Vertical Scroll Control (R11h)
R/W W RS 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
Rev. 1.0-1 / September 2002
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10
Figure 16 Vertical Scroll Control Instruction VL17-10: Specify the display-start raster-row at the 1st screen display for vertical smooth scrolling. Any raster-row from the first to 176th can be selected. After the 176th raster-row is displayed, the display restarts from the first raster-row. The display-start raster-row (VL17-10) is valid only when VLE1 = "1". The raster-row display is fixed when VLE1 = "0". (VLE1 is the 1st-screen vertical-scroll enable bit.) VL27-20: Specify the display-start raster-row at the 2nd screen display. The display-start raster-row (VL27-20) is valid only when VLE2 = "1". The raster-row display is fixed when VLE2 = "0". (VLE2 is the 1st-screen vertical-scroll enable bit.) Table 23
VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10 Display start line 1'st raster - row 2'nd raster - row 3'rd raster - row : 175'th raster row 176'th raster row -
0 0 0
:
0 0 0
:
0 0 0
:
0 0 0
:
0 0 0
:
0 0 0
:
0 0 1
:
0 1 0
:
1 1
0 0
1 1
0 0
1 1
1 1
1 1
0 1
Note: Do not set over the 176th ("AF"H)
raster - row
31
HD66766R
1st Screen Driving Position (R14h) 2nd Screen Driving Position (R15h)
R/W W RS 1
Rev. 1.0-1 / September 2002
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
W
1
SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
Figure 17 SS17-0: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the 'set value + 1' common driver. SE17-0: Specify the driving end position for the first screen in a line unit. The LCD driving is performed to the 'set value + 1' common driver. For instance, when SS17-10 = "07"H and SE17-10 = "10"H are set, the LCD driving is performed from COM8 to COM17, and non-selection driving is performed from COM1 to COM7, COM18 and others. Ensure that SS17-10 SE17-10 "AF"H. For details, see the Screen-division Driving Function section. SS27-0: Specify the driving start position for the second screen in a line unit. The LCD driving starts from the 'set value + 1' common driver. The second screen is driven when SPT = "1". SE27-0: Specify the driving end position for the second screen in a line unit. The LCD driving is performed to the 'set value + 1' common driver. For instance, when SPT = "1", SS27-20 = "20"H, and SE27-20 = "4F"H are set, the LCD driving is performed from COM33 to COM80. Ensure that SS17- 10 SE17-10 SS27-20 SE27-20 "AF"H. For details, see the Screen-division Driving Function section. Horizontal RAM Address Position (R16h) Vertical RAM Address Position (R17h)
R/W RS
W 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
W
1
VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
Figure 18 Horizontal/Vertical RAM Address Position Instruction HSA5-0/HEA5-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by HEA7-0 from the address specified by HSA5-0. Note that an address must be set before RAM is written to. Ensure 00h HSA7-0 HEA7-0 83h VSA7-0/VEA7-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by VEA7-0 from the address specified by VSA7-0. Note that an address must be set before RAM is written to. Ensure "00"h VSA7-0 VEA7-0 "AF"h.
32
HD66766R
HSA
0000h
Rev. 1.0-1 / September 2002
HEA
VSA
Window address setting range: "00"h HSA7-0 HEA7-0 "00"h VSA7-0 VEA7-0
Window Address
"83"h "AF"h
VEA
GRAM Address space AF83h
Figure 19 Window Address Setting Range Note: 1. Ensure that the window address area is within the GRAM address space. 2. In high-speed write mode, data are written to GRAM in four-words. Thus, dummy write operations should be inserted depending on the window address area. For details, see the High-Speed Burst RAM Write Function section.
RAM Write Data Mask (R20h)
R/W W RS 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB DB3 DB2 DB1 WM1 DB0 WM0
WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8
WM7 WM6 WM5 WM4 WM3 WM2
Figure 20 RAM Write Data Mask Instruction WM15-0: In writing to the GRAM, these bits mask writing in a bit unit. When WM15 = "1", this bit masks the write data of DB11 and does not write to the GRAM. Similarly, the WM10 to 0 bits mask the write data of DB15 to 0 in a bit unit. When HDZ = "1", mask processing is performed for 12-bit data after dither processing. For details, see the Write Data Mask Function section. RAM Address Set (R21h)
R/W W RS 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 AD15 AD14 AD13 AD12 AD11 AD10 AD9 DB8 AD8 DB7 AD7 DB6 AD6 DB5 AD5 DB4 AD4 DB3 AD3 DB2 AD2 DB1 AD1 DB0 AD0
Figure 21 RAM Address Set Instruction
AD15-0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written, the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive accesses without resetting addresses. Once the GRAM data is read, the AC is not automatically updated.
33
HD66766R
Rev. 1.0-1 / September 2002
GRAM address setting is not allowed in the standby mode. Ensure that the address is set within the specified window address. Table 24 GRAM Address Range AD15 to AD0 "0000"H to "0083"H "0100"H to "0183"H "0200"H to "0283"H "0300"H to "0383"H GRAM Setting Bitmap data for COM1 Bitmap data for COM2 Bitmap data for COM3 Bitmap data for COM4
"AC00"H to "AC83"H "AD00"H to "AD83"H "AE00"H to "AE83"H "AF00"H to "AF83"H
Bitmap data for COM173 Bitmap data for COM174 Bitmap data for COM175 Bitmap data for COM176
Write Data to GRAM (R22h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
1
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
Figure 22 Write Data to GRAM Instrction WD15-0 : Write 16-bit data to the GRAM; This data calls each grayscale palette. After a write, the address is automatically updated according to the AM and I/D bit settings. During the stand by mode, the GRAM cannot be accessed. GRAM write data during normal mode
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 WD4 DB3 DB2 DB1 DB0
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7
WD6 WD5
WD3 WD2
WD1 WD0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
1 pixcel
Figure 23
34
HD66766R
Table 25 GRAM data setting R4 G5 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R3 G4 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 R2 G3 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 R1 G2 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 R0 G1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PK05 PK15 PK25 PK35 PK45 PK55 PK65 PK75 PK85 PK95 PK105 PK115 PK125 PK135 PK145 PK155 PK165 PK175 PK185 PK195 PK205 PK215 PK225 PK235 PK245 PK255 PK265 PK275 PK285 PK295 PK305 G0
Rev. 1.0-1 / September 2002
Grayscale palette PK04 PK14 PK24 PK34 PK44 PK54 PK64 PK74 PK84 PK94 PK104 PK114 PK124 PK134 PK144 PK154 PK164 PK174 PK184 PK194 PK204 PK214 PK224 PK234 PK244 PK254 PK264 PK274 PK284 PK294 PK304 PK03 PK13 PK23 PK33 PK43 PK53 PK63 PK73 PK83 PK93 PK103 PK113 PK123 PK133 PK143 PK153 PK163 PK173 PK183 PK193 PK203 PK213 PK223 PK233 PK243 PK253 PK263 PK273 PK283 PK293 PK303 PK02 PK12 PK22 PK32 PK42 PK52 PK62 PK72 PK82 PK92 PK102 PK112 PK122 PK132 PK142 PK152 PK162 PK172 PK182 PK192 PK202 PK212 PK222 PK232 PK242 PK252 PK262 PK272 PK282 PK292 PK302 PK01 PK11 PK21 PK31 PK41 PK51 PK61 PK71 PK81 PK91 PK101 PK111 PK121 PK131 PK141 PK151 PK161 PK171 PK181 PK191 PK201 PK211 PK221 PK231 PK241 PK251 PK261 PK271 PK281 PK291 PK301 PK00 PK10 PK20 PK30 PK40 PK50 PK60 PK70 PK80 PK90 PK100 PK110 PK120 PK130 PK140 PK150 PK160 PK170 PK180 PK190 PK200 PK210 PK220 PK230 PK240 PK250 PK260 PK270 PK280 PK290 PK300
1 1 1 1 1 0 PK315 PK314 PK313 PK312 PK311 PK310 Note: When G0 = 1, selective grayscale for G pixel is the middle grayscale between the upper grayscale and the selective grayscale.
35
HD66766R
Read Data from GRAM (R22h)
R/W R RS 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Rev. 1.0-1 / September 2002
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2
RD1 RD0
Figure 24 Read Data from GRAM Instruction RD15-0: Read 16-bit data from the GRAM. When the data is read to the microcomputer, the first-word read immediately after the GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus (DB15-0) becomes invalid and the second-word read is normal.
Sets the I/D, AM, HSA/HSE, VSA/VEA Sets the I/D, AM, HSA/HSE, VSA/VEA
Address: N set
Address: N set
First word
Dummy read (invalid data) GRAM => Read data latch
First word
Dummy read (invalid data) GRAM => Read data latch
Second words
Read (data of address N) Read-data latch => DB11-0
Second words
Write (data of address N) DB11-0 = > GRAM
Address: M set
Automatic address update: N+
First word
Dummy read (invalid data) GRAM => Read data latch
First word
Dummy read (invalid data) GRAM => Read data latch
Second words
Read (data of address N) Read-data latch => DB11-0
Second words
Write (data of address N) DB11-0 => GRAM
i) Data read to the microcomputer
ii) Logical operation processing in the HD66766R
Figure 25 GRAM Read Sequence
36
HD66766R
Gray Scale Palette Control (R30h to R3Fh) Table 26 Grayscale Palette Control Instruction
R/W RS 1 1 1 1 DB15 0 0 0 0 DB14 DB13 0 0 0 0 PK 15 PK 35 PK 55 PK 75 PK 95 PK 115 PK 135 PK 155 PK 175 PK 195 PK 215 PK 235 PK 255 PK 275 PK 295 PK 315 DB12 DB11 DB10 DB9 PK 14 PK 34 PK 54 PK 74 PK 94 PK 114 PK 134 PK 154 PK 174 PK 194 PK 214 PK 234 PK 254 PK 274 PK 294 PK 314 PK 13 PK 33 PK 53 PK 73 PK 93 PK 113 PK 133 PK 153 PK 173 PK 193 PK 213 PK 233 PK 253 PK 273 PK 293 4 PK 313 PK 12 PK 32 PK 52 PK 72 PK 92 PK 112 PK 132 PK 152 PK 172 PK 192 PK 212 PK 232 PK 252 PK 272 PK 292 PK 312 PK 11 PK 31 PK 51 PK 71 PK 91 PK 111 PK 131 PK 151 PK 171 PK 191 PK 211 PK 231 PK 251 PK 271 PK 291 PK 311 DB8 PK 10 PK 30 PK 50 PK 70 PK 90 PK 110 PK 130 PK 150 PK 170 PK 190 PK 210 PK 230 PK 250 PK 270 PK 290 PK 310
Rev. 1.0-1 / September 2002
DB7 0 0 0 0
DB6 0 0 0 0
DB5 PK 05 PK 25 PK 45 PK 65 PK 85 PK 105 PK 125 PK 145 PK 165 PK 185 PK 205 PK 225 PK 245 PK 265 PK 285 PK 305
DB4 PK 04 PK 24 PK 44 PK 64 PK 84 PK 104 PK 124 PK 144 PK 164 PK 184 PK 204 PK 224 PK 244 PK 264 PK 284 PK 304
DB3 PK 03 PK 23 PK 43 PK 63 PK 83 PK 103 PK 123 PK 143 PK 163 PK 183 PK 203 PK 223 PK 243 PK 263 PK 283 PK 303
DB2 PK 02 PK 22 PK 42 PK 62 PK 82 PK 102 PK 122 PK 142 PK 162 PK 182 PK 202 PK 222 PK 242 PK 262 PK 282 PK 302
DB1 PK 01 PK 21 PK 41 PK 61 PK 81 PK 101 PK 121 PK 141 PK 161 PK 181 PK 201 PK 221 PK 241 PK 261 PK 281 PK 301
DB0 PK 00 PK 20 PK 40 PK 60 PK 80 PK 100 PK 120 PK 140 PK 160 PK 180 PK 200 PK 220 PK 240 PK 260 PK 280 PK 300
R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R3A R3B R3C R3D R3E R3F
W W W W
W W W W W
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
W W W
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
W W W W
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
PK31-0: Specify the grayscale level for thirty-two palettes from the 52-grayscale level. the Grayscale Palette and the Grayscale Palette Table sections.
For details, see
37
HD66766R
Instruction List (HD66766R)
Table 27
Upper Code
Reg. No. Register Name
Rev. 1.0-1 / September 2002
Lower Code DB DB DB DB DB DB 12 11 10 9 8 7 DB DB DB DB DB DB 6 5 4 3 2 1 DB 0 Description Exe cution Cyc le
0 0
Note1
R/ W
0 1
RS
DB DB DB 15 14 13
IR SR
Index Status read
0 0
* L7
* L6
* L5
* L4
* L3
* L2
* L1
* L0
* 0
ID6 C6
ID5 C5
ID4 C4
ID3 C3
ID2 C2
ID1 C1
ID0 C0
Sets the index register value. Reads the driving raster-row position (L7-0) and contrast setting (C6-0). Starts the oscillation mode.
R00h Start oscillation Device code read R01h Driver output control
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
10 ms 0
Note1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
Reads 0766H.
0
1
0
0
0
0
0
0
CM S
SGS
0
0
0
NL4
NL3
NL2
NL1
NL0 Sets the common driver shift direction (CMS), segment driver shift direction (SGS) and driving duty ratio (NL4-0). NW 0
0
R02h LCDdrivingwaveform control R03h Power control 1
0
1
0
0
0
0
0
RST
B/C
EOR
0
0
NW 5
NW 4
NW 3
NW 2
NW 1
0 Sets LCD drive AC waveform (B/C), and EOR output (EOR) or the number of n-raster-rows (NW5-0) at C-pattern AC drive. 0
0
1
BS3
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
DC2 DC1 DC0 AP1
AP0
SLP
STB Sets the sleep mode (SLP), standby mode (STB), LCD power on (AP1- 0), boosting cycle (DC2-0), boosting output multiplying factor (BT2-0), operation of voltage inverting circuit (BT3) and LCD drive bias value (BS3-0).
R04h Contrast control R05h Entry mode
0
1
0
0
0
0
0
VR2 VR1 VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0 Sets the regulator adjustment (VR2- 0 0) and contrast adjustment (CT6-0). LG0 Specifies AC counter mode (AM), increment/decrement mode (I/D1- 0), high-speed write mode (HWM). CP0 Specifies the compare resister (CP15-0), D0 Specifies display on (D1-0), blackand-white reversed display (REV), pixel on/off mode (ALB), screen division driving (SPT) and vertical scroll .(VLE2-1) 0
Note2
0
1
SPR
0
0
0
0
0
HWM
0
0
0
I/D1
I/D0
AM
LG2
LG1
R06h Compare Resister R07h Display control
0
1
CP1 5 0
CP1 4 0
CP1 3 0
CP1 2 0
CP1 1 0
CP1 0
VLE2
CP9
CP8
CP7
CP6
CP5
CP4
CP3
CP2
CP1
0
0
1
VLE1
SPT
0
0
0
0
B/W REV
D1
0
R0Bh Frame frequency control R0Ch Power control 2 R11h Vertical scroll control
0
1
0
0
0
0
0
0
DIV 1
DIV 0
0
0
0
0
RTN RTN RTN RTN Specifies the line retrace period 3 2 1 0 (RTN3-0) and operating clock frequency division ratio (DIV1-0). 0 VC2 VC1 VC0 Sets the adjustment factor for the Vci voltage (VC2-0). VL1 2 VL1 1 VL1 0 Sets the 1 st screen display start raster- row (VL17-10) and 2nd screen display start raster-row (VL27-20). Sets the 1st screen driving start position (SS17-10) and 1 st screen driving end position (SE17-10). Sets 2 nd screen driving start position (SS27-20) and 2 nd screen driving end position (SE27-20).
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
VL2 7
VL2 6
VL2 5
VL2 4
VL2 3
VL2 2
VL2 1
VL2 0
VL1 7
VL1 6
VL1 5
VL1 4
VL1 3
0
R14h 1st screen driving position R15h 2nd screen driving position R16h Horizontal RAM address position R17h Vertical RAM address position R20h RAM write data mask
0
1
SE 17
SE 16
SE 15
SE 14
SE 13
SE 12
SE 11
SE 10
SS 17
SS 16
SS 15
SS 14
SS 13
SS 12
SS 11
SS 10
0
0
1
SE 27
SE 26
SE 25
SE 24
SE 23
SE 22
SE 21
SE 20
SS 27
SS 26
SS 25
SS 24
SS 23
SS 22
SS 21
SS 20
0
0
1
HE A7
HEA HEA HEA HEA HEA HEA HEA HSA HSA HSA HSA HSA HSA HSA HSA Sets start (HSA7-0) and end 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 (HEA7-0) of the horizontal RAM address range.
0
0
1
VEA VEA VEA VEA VEA VEA VEA VEA VSA VSA VSA VSA VSA VSA VSA VSA Sets start (VSA7-0) and end 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 (VEA7-0) of the vertical RAM address range.
0
0
1
WM 15
WM 14
WM 13
WM 12
WM 11
WM 10
WM 9
WM 8
WM 7
WM 6
WM 5
WM 4
WM 3
WM 2
WM 1
WM Specifies write data mask (WM15- 0) at RAM write. 0
0
38
HD66766R
Instruction List (cont.)
Upper Code Lower Code
Rev. 1.0-1 / September 2002
Reg. No.
Register Name
R/ W
0
RS
1
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0 Description
Initially set the RAM address to the address counter (AC). Writes data to the RAM.
Execution Cycle
0
R21h RAM address set R22 RAM data write RAM data read R30h Grayscale palette control (1) R31h Grayscale palette control (2) R32h Grayscale palette control (3) R33h Grayscale palette control (4) R34h Grayscale palette control (5) R35h Grayscale palette control (6) R36h Grayscale palette control (7) R37h Grayscale palette control (8) R38h Grayscale palette control (9) R39h Grayscale palette control (10) R3Ah Grayscale palette control (11) R3Bh Grayscale palette control (12) R3Ch Grayscale palette control (13) R3Dh Grayscale palette control (14) R3Eh Grayscale palette control (15) R3Fh Grayscale palette control (16)
AD15-8 (upper)
AD6-0 (lower)
0
1
Write data (upper)
Write data (lower)
0
1
1
Read data (upper)
Read data (lower)
Reads data from the RAM.
0
0
1
0
0
PK15 PK14 PK13 PK12 PK11 PK10
0
0
PK05 PK04 PK03 PK02 PK01 PK00 Specifies the grayscale palette.
0
0
1
0
0
PK35 PK34 PK33 PK32 PK31 PK30
0
0
PK25 PK24 PK23 PK22 PK21 PK20 Specifies the grayscale palette.
0
0
1
0
0
PK55 PK54 PK53 PK52 PK51 PK50
0
0
PK45 PK44 PK43 PK42 PK41 PK40 Specifies the grayscale palette.
0
0
1
0
0
PK75 PK74 PK73 PK72 PK71 PK70
0
0
PK65 PK64 PK63 PK62 PK61 PK60 Specifies the grayscale palette.
0
0
1
0
0
PK95 PK94 PK93 PK92 PK91 PK90
0
0
PK85 PK84 PK83 PK82 PK81 PK80 Specifies the grayscale palette.
0
0
1
0
0
PK 115
PK 114 PK 134 PK 154 PK 174 PK 194 PK 214 PK 234 PK 254 PK 274 PK 294 PK 314
PK 113 PK 133 PK 153 PK 173 PK 193 PK 213 PK 233 PK 253 PK 273 PK 293 PK 313
PK 112 PK 132 PK 152 PK 172 PK 192 PK 212 PK 232 PK 252 PK 272 PK 292 PK 312
PK 111 PK 131 PK 151 PK 171 PK 191 PK 211 PK 231 PK 251 PK 271 PK 291 PK 311
PK 110 PK 130 PK 150 PK 170 PK 190 PK 210 PK 230 PK 250 PK 270 PK 290 PK 310
0
0
PK 105
PK 104 PK 124 PK 144 PK 164 PK 184 PK 204 PK 224 PK 244 PK 264 PK 284 PK 304
PK 103 PK 123 PK 143 PK 163 PK 183 PK 203 PK 223 PK 243 PK 263 PK 283 PK 303
PK 102 PK 122 PK 142 PK 162 PK 182 PK 202 PK 222 PK 242 PK 262 PK 282 PK 302
PK 101 PK 121 PK 141 PK 161 PK 181 PK 201 PK 221 PK 241 PK 261 PK 281 PK 301
PK 100 PK 120 PK 140 PK 160 PK 180 PK 200 PK 220 PK 240 PK 260 PK 280 PK 300
Specifies the grayscale palette.
0
0
1
0
0
PK 135
0
0
PK 125
Specifies the grayscale palette.
0
0
1
0
0
PK 155
0
0
PK 145
Specifies the grayscale palette.
0
0
1
0
0
PK 175
0
0
PK 165
Specifies the grayscale palette.
0
0
1
0
0
PK 195
0
0
PK 185
Specifies the grayscale palette.
0
0
1
0
0
PK 215
0
0
PK 205
Specifies the grayscale palette.
0
0
1
0
0
PK 235
0
0
PK 225
Specifies the grayscale palette.
0
0
1
0
0
PK 255
0
0
PK 255
Specifies the grayscale palette.
0
0
1
0
0
PK 275
0
0
PK 265
Specifies the grayscale palette.
0
0
1
0
0
PK 295
0
0
PK 285
Specifies the grayscale palette.
0
0
1
0
0
PK 315
0
0
PK 305
Specifies the grayscale palette.
0
Note:
1. "*" means doesn't matter. 2. High-speed write mode is available only for the RAM writing.
39
HD66766R
Reset Function
Rev. 1.0-1 / September 2002
The HD66766R is internally initialized by RESET input. Reset the gate driver/Power supply IC as its settings are not automatically reinitialized when the HD66766R is reset. The reset input must be held for at least 200 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms).
Instruction Set Initialization:
1. 2. 3. 4. Start oscillation executed Driver output control (NL4-0 = "10101", SGS = "0", CMS = "0") B-pattern waveform AC drive (B/C = "0", EOR = "0", NW5-0 = "000000") Power control 1 (DC2-0 = "000", AP1-0 = "00": LCD power off, STB = "0": Standby mode off, SLP = "0", BS2-0 = "000", BT2-0 = "000") 5. Contrast control (Weak contrast VR3-0 = "0000", CT6-0 = "0000000") 6. Entry mode set ( SPR= "0" , HWM = "0", I/D1-0 = "11": Increment by 1, AM = "0": Horizontal move, LG2-0="000":Replace mode ) 7. Compare resister : (CP15-0 = "0000000000000000" 8. Display control (VLE2-1 = "00": No vertical scroll, SPT = "0", REV = "0", D1-0 = "00": Display off) 9. Frame cycle control (DIV1-0 = "00": 1-divided clock, RTN3-0: No line retrace period) 10. Power control 2 (VC2-0 = "000") 11. Vertical scroll (VL27-20 = "00000000", VL17-10 = "00000000") 12. 1st screen division (SE17-10 = "11111111", SS17-10 = "00000000") 13. 2nd screen division (SE27-20 = "11111111", SS27-20 = "00000000") 14. Horizontal RAM address position (HEA7-0 = "10000011", HSA7-0 = "00000000") 15. Vertical RAM address position (VEA7-0 = "10101111", VSA7-0 = "00000000") 16. RAM write data mask (WM11-0 = "000"H: No mask) 17. RAM address set (AD15-0 = "0000"H) 18. Grayscale Palette (PK0 = "000000", RK1= "000011", PK2= "000110", PK3= "001000 ", PK4= "001010", PK5= "001100", PK6= "001110", PK7= "001111", PK8= "010000", PK9= "010001", PK10= "010010", PK11= "010011", PK12= "010100", PK13= "010101", PK14= "010110", PK15= "010111", PK16 = "011000", PK17= "011001", PK18= "011010", PK19= "011011", PK20= "011100", PK21= "011101", PK22= "011110", PK23= "100000", PK24= "100010", PK25= "100100", PK26= "100110", PK27= "101000" , PK28 = "101011", PK29= "101110", PK30= "110001", PK31= "110100",)
GRAM Data Initialization: This is not automatically initialized by reset input but must be initialized by software while display is off (D1-0 = "00"). Output Pin Initialization: 1. LCD driver output pins (SEG/COM): Output GND level 2. Oscillator output pin (OSC2): Output oscillation signal
40
HD66766R
Parallel Data Transfer
16-bit Bus Interface
Rev. 1.0-1 / September 2002
Setting the IM2/1/0 (interface mode) to the "GND"/"GND"/"GND" level allows 68-system E-clocksynchronized 16-bit parallel data transfer. Setting the IM2/1/0 to the "GND"/"Vcc"/"GND" level allows 80-system 16-bit parallel data transfer. When the number of buses or the mounting area is limited, use an 8-bit bus interface.
CSn* A1 HWR* (RD*) D15 - D0 CS* RS WR* (RD*)
H8/2245
HD66766
DB15 - DB0
16 Figure 26 Interface to 16-bit Microcomputer 8-bit Bus Interface Setting the IM2/1/0 (interface mode) to the "GND"/"GND" /"Vcc" level allows 68-system E-clocksynchronized 8-bit parallel data transfer using DB15-DB8 pins. Setting the IM2/1/0 to the "GND"/"Vcc"/"Vcc" level allows 80-system 8-bit parallel data transfer. The 16-bit instructions and RAM data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7-DB0 to the "Vcc" or "GND" level. Note that the upper bytes must also be written when the index register is written to.
CSn* A1 H8/2245 HWR* (RD*) D15 - D8 8 8
GND
CS* RS WR* HD66766 (RD*) DB15 - DB8 DB7 - 0
Figure 27 Interface to 8-bit Microcomputer
41
HD66766R
Note:
Rev. 1.0-1 / September 2002
Transfer synchronization function for an 8-bit bus interface The HD66766R supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a "00"H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system
RS R/W E
DB15 to DB8
Upper or lower
"00"H
"00"H
"00"H
"00"H
Upper Lower
(1)
(2)
(3)
(4)
8-bit transfer synchronization
Figure 28 8-bit Transfer Synchronization
42
HD66766R
Serial Data Transfer
Rev. 1.0-1 / September 2002
Setting the IM2 pin to the "Vcc" level and the IM1 pin to the "GND" level allows standard clocksynchronized serial data transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data line (SDI), and serial output data line (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at "Vcc" or "GND". The HD66766R initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It ends serial data transfer at the rising edge of CS* input. The HD66766R is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66766R. The HD66766R, when selected, receives the subsequent data string. The least significant bit of the identification code can be determined by the ID pin. The five upper bits must be "01110". Two different chip addresses must be assigned to a single HD66766R because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = "0", data can be written to the index register or status can be read, and when RS = "1", an instruction can be issued or data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is "0", and is transmitted when the R/W bit is "1". After receiving the start byte, the HD66766R receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All HD66766R instructions are 16 bits. Two bytes are received with the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. Five bytes of RAM read data after the start byte are invalid. data from the sixth byte. Table 28 Start Byte Format
Transfer Bit Start byte format Note: S Transfer start 1 2 3 4 5 6 7 RS 8 R/W
The HD66766R starts to read correct RAM
Device ID code 0 1 1 1 0 ID
The IM0/ID pin selects ID bit.
Table 29 RS and R/W Bit Function
RS 0 0 1 1 R/W 0 1 0 1 Function Sets index register Reads status Writes instruction or RAM data Reads RAM data
43
HD66766R
Transfer start CS* (input)
Rev. 1.0-1 / September 2002
Transfer end
a) Timing of basic data-transfer through clock synchronized serial interface
1234
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDI (input)
"0"
MSB
"1" "1" "1" "0" D RS RW DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 15 14 13 12 11 10 9 8 7654321
LSB
DB 0
Device D code Start byte SDO (output)
RS RW
index register instruction / GRAM write data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 15 14 13 12 11 10 9 8 7654321 DB 0
Status read / Ram read
Figure 29 Procedure for transfer through the clock synchronized serial inrface (a) b) Timing of consecutive data transfer through clock synchronized serial interface
CS (input) SCL (input) SDI (input) Start The first byte after start byte must be upper 8-bit. Instruction is not executed.
Instruction(1) upper 8-bit Instruction(1) lower 8-bit Instruction(2) upper 8-bit 12 345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2930 31 32
Start byte
Instruction (1) execution time
"End"
Figure 30 Procedure for transfer through the clock synchronized serial interface (b)
44
HD66766R
C) Transfer data read from GRAM
CS* (input) SCL (input) SDI (input)
Start byte RS="1" R/W="1"
Rev. 1.0-1 / September 2002
SDO (output) "Start"
Dummy read (1)
Dummy read (2)
Dummy read (3)
Dummy read (4)
Dummy read (5)
RAM read upper 8-bit
RAM read lower 8-bit
Five bytes invalid dummy data are read after start byte. 6th data is valid from GRAM.
"End"
Figure 31 Procedure for transfer through the clock synchronized serial interface (c)
d) Status Read / Instruction Read
CS* (input) SCL (input) SDI (input)
Start byte RS="0" R/W="1"
SDO (output)
Dummy read (1)
Status read upper 8-bit
Status read lower 8-bit
"Start"
"End" One byte invalid dummy data are read after start byte. 2nd data is valid from GRAM.
Figure 32 Procedure for transfer through the clock synchronized serial interface (d)
45
HD66766R
High-Speed Burst RAM Write Function
Rev. 1.0-1 / September 2002
The HD66766R has a high-speed burst RAM-write function that can be used to write data to RAM in one-fourth the access time required for an equivalent standard RAM-write operation. This function is especially suitable for applications that require the high-speed rewriting of the display data, for example, display of color animations, etc. When the high-speed RAM-write mode (HWM) is selected, data for writing to RAM is once stored to the HD66766R internal register. When data is selected four times per word, all data is written to the on-chip RAM. While this is taking place, the next data can be written to an internal register so that high-speed and consecutive RAM writing can be executed for animated displays, etc.
Microcomputer
16
Address counter (AC)
Resistor 1
Resistor 2
Resistor 3
48
Resistor 4
16 "0000"H "0001"H "0002"H "0003"H
GRAM
Figure 33 Flow of Operation in High-Speed Consecutive Writing to RAM
CS* (input) 1 2 3 4 1 2 3 4 1 2 3 4
DB15-0 (input / output)
Index (R22)
RAM RAM R4M RAM RAM RAM RAM RAM RAM RAM RAM RAM data data data data data data data data data data data data (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12)
Index (R22)
RAM write execution time *
RAM write execution time
RAM write execution time
RAM write data (48 bit) RAM address (AC15 to 0)
RAM data 1 to 4
RAM data 5 to 8
RAM data 9 to 12
"0000"H
"0004"H
"0008"H
"000A"H
* The lower two bits of the address must be set in the following way in high-speed write mode. When D0 becomes 0, the lower two bits of the address must be set to "11". Wen D1 becomes 1, the lower two bits of the address must be set to "00". Note: When a high-speed RAM write is canceled, the next instruction must only be executed after the RAM write execution time has elapsed.
Figure 34 Example of the Operation of High-Speed Consecutive Writing to RAM
46
HD66766R
Note the following when using high-speed RAM write mode.
Rev. 1.0-1 / September 2002
Notes: 1. The logical and compare operation cannot be used. 2. Data is written to RAM each four words. When an address is set, the lower two bits in the address must be set to the following values. *When I/D0=0, the lower two bits in the address must be set to "11" and be written to RAM. *When I/D0=1, the lower two bits in the address must be set to "00" and be written to RAM. 3. Data is written to RAM each four words. If less than four words of data is written to RAM, the last data will not be written to RAM. 4. When the index register and RAM data write ("22"H) have been selected, the data is always written first. RAM cannot be written to and read from at the same time. HWM must be set to "0" while RAM is being read. 5. High-speed and normal RAM write operations cannot be executed at the same time. The mode must be switched and the address must then be set. 6. When high-speed RAM write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. Refer to the HighSpeed RAM Write in the Window Address section.
Table 30 Comparison between Normal and High-Speed RAM Write Operations
Normal RAM Write (HWM=0) Can be used Can be used Can be used Can be specified by word Can be read by word Can be written by word Can be set by word High-Speed RAM Write (HWM=1) Cannot be used Cannot be used Can be used ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 Cannot be used Dummy write operations may have to be inserted according to a window addressrange specification Can be set by four words
Logical operation function Compare operation function Write mask function RAM address set RAM read RAM write Window address
47
HD66766R
High-Speed RAM Write in the Window Address
Rev. 1.0-1 / September 2002
When a window address range is specified, RAM data which is in an optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts become 4N as shown in the tables below. Dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0). The number of dummy write operations of a row must be 4N. Table 31 Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
HSA1 0 0 1 1 HSA0 0 1 0 1 Number of Dummy Write Operations to be Inserted at the Start of a Row 0 1 2 3
Table 32 Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
HEA1 0 0 1 1 HEA0 0 1 0 1 Number of Dummy Write Operations to be Inserted at the End of a Row 3 2 1 0
Each row of access must consist of 4 x N operations, including the dummy writes. Horizontal access count = first dummy write count + write data count + last dummy write count = 4 x N
48
HD66766R
Rev. 1.0-1 / September 2002
An example of high-speed RAM write with a window address-range specified is shown below. The window address-range can be rewritten to consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (HSA1 to 0= "10", HEA1 to 0= "00").
Writing in the horizontal direction AM=0, I/D0=1 Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0 High-speed RAM write mode setting HWM=1
h0000 h0812
GRAM address map
Window address-range specification (rewrite area)
Address set AD=h0810
hA030
Note 1)
hAF83
Dummy RAM write x 2
Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0 x 152
RAM write x 31
Dummy RAM write x 3 Note1) The address set for the high-speed RAM write must be 00 or 11 according to the value of I/D0 bit. Only RAM in the speicfied window address-range will be overwritten.
Figure 35 Example of the High-Speed RAM write with a window address-range specification
49
HD66766R
Window Address Function
Rev. 1.0-1 / September 2002
When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end: VEA70) can be written to consecutively. Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. The window must be specified to be within the GRAM address area described below. Addresses must be set within the window address. [Restriction on window address-range settings] (horizontal direction) "00"H HSA7-0 HEA7-0 "83"H (vertical direction) "00"H VSA7-0 VEA7-0 "AF"H [Restriction on address settings during the window address] (RAM address) HSA7-0 AD7-0 HEA7-0 VSA7-0 AD15-8 VEA7-0 Note: In high-speed RAM-write mode, the lower two bits of the address must be set as shown below according to the value of the ID0 bit. ID0=0: The lower two bits of the address must be set to "11". ID0=1: The lower two bits of the address must be set to "00"
GRAM address map 0000H Window address area 2010H 2110H 0083H
202FH 212FH
5F10H
5F2FH
AF00H Window address-range specification area HSA5-0=10H, HSE5-0=2FH VSA7-0=20H, VEA7-0=5FH
AF83H
I/D0=1 (increment) AM=0 (horizontal writing)
Figure 36 Example of Address Operation in the Window Address Specification
50
HD66766R
Graphic Operation Function
Rev. 1.0-1 / September 2002
The HD66766R can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. This function supports the following:
1. 2. A write data mask function that selectively rewrites some of the bits in the 16-bit write data. A conditional write function that compares the write data and compare-bit data and writes the data sent from the microcomputer only when the conditions match. Even if the display size is large, the display data in the graphics RAM ( GRAM ) can be quickly rewritten. The graphics bit operation can be controlled by combining the entry mode resister. The bit set value of the RAM-write -data mask resister, and the write from the microcomputer.
Bit Setting Operation Mode Write mode 1 Write mode 2 Write mode 3 Write mode 4 I/D 0 /1 0 /1 0 /1 0 /1 AM 0 1 0 1 LG2-0 000 000 110,111 110,111 Operation and Usage Horizontal data replacement, horizontal - border drawing Vertical data replacement, vertical - border drawing Conditional horizontal data replacement, horisontal - border drawing Conditional vertical data replacement, vertical - border drawing
Table 33 Graphics operation
Microcomputer 16
Write data latch
+1/-1
+ 256
16
Address counter ( AC )
3
Logical / compare operation (LG2 - 0:) 000: replacement bit. 110: replacement with matched write, Only replacement with unmatched write RAM in the 111: 16 16 Write bit mask 16
Logical operation bit ( LG2 - 0 ) Compare bit ( CP7 - 0 )
Write mask register ( WM15 - 0 )
16
Graphic RAM ( GRAM )
Figure 37 Graphics Operation flow
51
HD66766R
Write-data Mask Function
Rev. 1.0-1 / September 2002
The HD66766R has a bit-wise write-data mask function that controls writing the 16-bit data from the microcomputer to the GRAM. Bits that are "0" in the write-data mask register (WM15-0) cause the corresponding DB bit to be written to the GRAM. Bits that are "1" prevent writing to the corresponding GRAM bit to the GRAM; the data in the GRAM is retained. This function can be used when only onepixel data is rewritten or the particular display color is selectively rewritten.
DB15 Data written by the microcomputer R04 R03 R02 WM15 Write data mask 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 R01 R00 G05 G04 G03 G02 G01 G00 B04 B03 B02 B01 DB0 B00 WMO 0
DB11 GRAM data * * * * * G05 G04 G03 G02 G01 * * * B02 B01
DB0 B00
Figure 38 Write-data Mask Function Operation
52
HD66766R
Graphics Operation Processing
1. Write mode 1: AM = 0, LG2-0 = "000"
Rev. 1.0-1 / September 2002
This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM ( GRAM ) or to draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments by 1 ( I/D = 1 ) or decrements by 1 ( I/D = 0 ) , and automatically jumps to the counter edge one-raster below after it has reached the left or right edge of the GRAM.
Operation Examples: 1) I/D = "1", AM = "0", LG2-0 = "000" 2) WM15-0 = "07FF"H 3) AC = "0000"H WM15 Write data mask: 0 DB15 Write data (1) : Write data (2) : WM0 "Write mask for plane G and B.
000011111111111 DB0
1001111110010100 1100000000110000 "0000"H "0001"H 11000*********** Write data (2) GRAM Note: The bits in the GRAM indicated by (*) are not changed. "0002"H
10011*********** Write data (1)
Figure 39 Writing Operation of Write Mode 1
53
HD66766R
2. Write mode 2: AM = 1, LG2-0 = "000"
Rev. 1.0-1 / September 2002
This mode is used when the data is vertically written at high speed. It can also be used to initialize the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments by 256, and automatically jumps to the upper-right edge ( I/D =1 ) or upperleft egde ( I/D = 0 ) following the I/D bit after it has reached the lower edge of the GRAM.
Operation Examples: 1) I/D = "1" , AM = "1", 2) WM15-0 = "07FF"H 3) AC = "0000"H WM15 000 Write- data mask: DB15 Write data (1): Write data (2): Write data (3): "0000"H "0100"H "0200"H
10011*********** 11000***********
LG2-0 = "000"
WM0
0011111111111
DB0
1001111110010100 1100000000 11 0000 0111110001000001
Write data (1) Write data (2) Write data (3)
01111***********
GRAM
Notes: 1. The bit area data in the GRAM indicated by (*) is not changed. 2. After writing to address "AF00"H the AC jumps to "0001"H.
Figure 40 Operation of Write Mode 2
54
HD66766R
3. Write mode 3: AM = 0, LG2-0 = 110/111
Rev. 1.0-1 / September 2002
This mode is used when the data is holizontally written by comparing the write data and the set value of the compare resister ( CP7-0 ). When the result of the comparison in a byte unit satisfies the condition write-data mask function ( WM15-0 ) are also enabled. After writing , the address counter ( AC ) automatically increments by 1 ( I/D =1 ) or decrements by 1 ( I/D = 0 ), and automatically jumps to the counter edge one-raster-raw below after it has reached the left or right edge of the GRAM.
Operation Examples: 1) I/D = "1", AM = "0" , 2) CP15-0 = "2860"H 2) WM15-0 = "0000"H 3) AC = "0000"H
LG2-0 = "110" ( Matched write )
WM15 Write - data mask :
WM0
0 0 0 0 0 0 0 0 0 00 0 00 0 0 CP15 CP0
Compare register :
Compare operation
001 010 00 011 00 000 (Matched) Conditional replacement C R 001 010 00 011 00 000 Replacement
DB15 Write data (1) :
DB0
001 0 1000 01 100 00 0
Compare operation Conditional replacement Write data (2) : 000 001 11 1110 000 0 C R
* ** ** ** * * ** * * ** *
"0000"H 001 0 1000 01 100 00 0 Matched replacement of write data (1)
"0001"H ** * * ** ** ** ** * ** *
GRAM
Figure 41 Operation of Write Mode 3
55
HD66766R
4. Write mode 4: AM = 1, LG2-0 = 110/111
Rev. 1.0-1 / September 2002
This mode is used when a vertical comparison is performed between the write data and the set value of the compare resister ( CP15-0 ) to write the data . When the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, write data mask function ( WM15-0 ) are also enabled. After writing, the address counter ( AC ) automatically increments by 256, and automatically jumps to the upper-right edge ( I/D = 1) or upper-left edge ( I/D = 0 ) following the I/D bit after it has reached the lower edge of the GRAM.
Operation Examples: 1) I/D = "1", AM = "1" , 2) WM15-0 = "0000"H 2) CP15-0 = "2860"H 3) AC = "0000"H WM15 Write - data mask : WM0
LG2-0 = "111" ( Unmatched write )
0 0 0 0 0 0 0 00 0 0 00 0 0 0 CP15 CP0
Compare operation
Compare register :
0 0 1 0 1 0 0 00 1 1 0 0 0 0 0 DB15 ( Unmatched ) DB0 C Conditional replacement R 1 0 0 1 1 0 0 11 0 0 1 1 1 1 1
Write data (1) :
1 0 0 1 1 0 0 11 0 0 1 1 1 1 1
Compare operation ( Unmatched ) Write data (2) : 0 0 1 0 1 0 0 00 1 1 0 0 0 0 0 C Conditional replacement R **** ** * **** **** *
"0000"H "0000"H "0100"H
"0001"H
1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 Write data (1) * * * * * * * * * * * * * * * * Write data (2) GRAM
"AF00"H Notes: 1. The bit area data in the GRAM indicated by (*) is not changed. 2. After writing to address "AF00"H the AC jumps to "0001"H.
Figure 42 Writing Operation of Write Mode 4
56
HD66766R
4096 colors Display Function
Rev. 1.0-1 / September 2002
HD66766R is equipped with 4096 colors display function. When setting SPR bit = 1, it operates 4096 color display function, and uses 16 bits instead of 12 bits. Upper 4 bits are invalid when operating 4096 colors display function. While operating 4096 colors display function, write mode 3 and 4 in graphic operation are not usable.
GRAM 46,464 byte
DB15
RAM write data 65k format
RAM write DB0 DB15
RAM read data 65k format
RAM read DB0
R4 R3 R2 R1 R0 G5 G 4 G3 G 2G 1G0 B4 B3 B2 B1 B0
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
DB15
0 0 0 0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
DB0
DB15
0 00
DB0
0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
Write data 4096 color format
Read data 4096 color format
Figure 43 4096 color display data write and read format
Table 34 4,096 color R, G, B data and selective grayscale palette R, G, B data 0000 0001 0010 0011 0100 0101 0110 0111 Selective grayscale palette PK0 PK2 PK4 PK6 PK8 PK10 PK12 PK14 R, G, B data 1000 1001 1010 1011 1100 1101 1110 1111 Selective grayscale palette PK17 PK19 PK21 PK23 PK25 PK27 PK29 K31
57
HD66766R
Grayscale Palette
Rev. 1.0-1 / September 2002
The HD66766R incorporates a grayscale palette to simultaneously display 65K of the 140,608 possible colors. The grayscales consist of 32 6-bit palettes. The 52-stage grayscale levels can be selected from the 6-bit palette data. For the display data, the four-bit data in the GRAM written from the microcomputer is used. In this palette, a pulse-width control system (PWM) is used to eliminate flicker in the LCD display. The time over which the LCDs are switched on is adjusted according to the level and grayscales are displayed so that flicker is reduced and grayscales are clearly displayed.
Graphic RAM ( GRAM ) M SB LSB
Display data Palette
PK0 (5*0)
R4
R3
R2 5
R1
R0
G5
G4
G3
G2 6
G1
G0
B4
B3
B2 5
B1
B0
"00000" "00001" "00010" "00011" "00100" "00101" "00110"
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 0 1
0 0
0 0
0 1 1 0 1 0 1 1 0 0 1
0 1 0 0 0 0 0 1 0 1 0
"01011"
" 01100"
PK11 (5*0)
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 1 1 0 0 1 1 0 0
1 0 0 0 1 0 1 0 1 0 1
"10110" "10111" "11000" "11001" "11010" "11011" "11100"
PK22 (5*0)
0 1 1 1 1 1 1
1 0 0 0 0 0 0 0 1 1
1 0 0 0 0 1 1 1 0
PK31 (5*0)
1 0 0 1 1 0 0 1 0 1
1 0 1 0 1 0 1 1 0 0
0 0 0 0 0 0 1 0 1 0
PK1 (5*0) PK2 (5*0) PK3 (5*0)
PK12 (5*0) PK13 (5*0) PK14 (5*0) PK15 (5*0) PK16 (5*0) PK17(5*0) PK18 (5*0)
PK23 (5*0) PK24 (5*0) PK25 (5*0) PK26 (5*0) PK27 (5*0) PK28(5*0) PK29 (5*0)
"01101" "01110" "01111" "10000" "10001" "10010" "10011" "10100" "10101"
0 1
1 0 0
PK4 (5*0)
1 1 1
PK5 (5*0)
1 1
PK6(5*0) PK7 (5*0)
"00111" "01000" "01001" "01010"
0 0 0
1 0 0 0
1 0 0 0
"11101" "11110" "11111"
PK8 (5*0) PK9 (5*0) PK10 (5*0)
1 1 1
PK19 (5*0)
PK30 (5*0)
1 1 1
0 1 1
PK20 (5*0) PK21 (5*0)
0
Palette register Initialized value
6 5 5 52 gray scale control
32
5
52 gray scale control 32 LCD Driver
1
52 gray scale control 32
32
* 64 gray scale
64
LCD Driver
LCD Driver
R
G
LCD
B
Figure 44 Grayscale Palette Control
58
HD66766R
Grayscale Palette Table
Rev. 1.0-1 / September 2002
The grayscale register that is set for each palette register (PK) can be set to any level. 52-grayscale lighting levels can be set according to palette values ("000000" to "110100"). Table 35 Grayscale Control Level
Palette Register Value (PK) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Grayscale Control Level Unlit level*1 1/52level 2/52level 3/52level 4/52level 5/52level 6/52level 7/52level 8/52level 9/52level 10/52level 11/52level 12/52level 13/52level 14/52level 15/52level 16/52level 17/52level 18/52level 19/52level 20/52level 21/52level 22/52level 23/52level 24/52level 25/52level 26/52level 27/52level 28/52level 29/52level 30/52level 31/52level 32/52level
a Next Page continued
59
HD66766R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
Rev. 1.0-1 / September 2002
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 33/52level 34/52level 35/52level 36/52level 37/52level 38/52level 39/52level 40/52level 41/52level 42/52level 43/52level 44/52level 45/52level 46/52level 47/52level 48/52level 49/52level 50/52level 51/52level All lit level*2
Notes: 1. The unlit level corresponds to a black display when a normally-black color-LCD panel is used, and a white display when a normally-white color-LCD panel is used. 2. The all-lit level corresponds to a white display when a normally-black color-LCD panel is used, and a black display when a normally-white color-LCD panel is used
60
HD66766R
RGB pixel data and Grayscale level Table 36 G pixel data and output level
Rev. 1.0-1 / September 2002
G pixel data
000000 000001 000010 000011 000100 000101 000110 0000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 0100001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
Output level PK0 (PK0+PK1)/2 PK1 (PK1+PK2)/2 PK2 (PK2+PK3)/2 PK3 (PK3+PK4)/2 PK4 (PK4+PK5)/2 PK5 (PK5+PK6)/2 PK6 (PK6+PK7)/2 PK7 (PK7+PK8)/2 PK8 (PK8+PK9)/2 PK9 (PK9+PK10)/2 PK10 (PK10+PK11)/2 PK11 (PK11+PK12)/2 PK12 (PK12+PK13)/2 PK13 (PK13+PK14)/2 PK14 (PK14+PK15)/2 PK15 (PK15+PK16)/2
G pixel data
100000 100001 100010 100011 100100 100101 10110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
Output level
PK16 (PK16+PK17)/2 PK17 (PK17+PK18)/2 PK18 (PK18+PK19)/2 PK19 (PK19+PK20)/2 PK20 (PK20+PK21)/2 PK21 (PK21+PK22)/2 PK22 (PK22+PK23)/2 PK23 (PK23+PK24)/2 PK24 (PK24+PK25)/2 PK25 (PK25+PK26)/2 PK26 (PK26+PK27)/2 PK27 (PK27+PK28)/2 PK28 (PK28+PK29)/2 PK29 (PK29+PK30)/2 PK30 (PK30+PK31)/2 PK31 PK31
61
HD66766R
Table 37 R, B pixel data and output level
Rev. 1.0-1 / September 2002
R, B pixel data
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
Output level PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PK8 PK9 PK10 PK11 PK12 PK13 PK14 PK15
R, B pixel data 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Output level PK16 PK17 PK18 PK19 PK20 PK21 PK22 PK23 PK24 PK25 PK26 PK27 PK28 PK29 PK30 PK31
62
HD66766R
Sleep Mode
Rev. 1.0-1 / September 2002
Setting flow for low power consumption instruction
Setting the sleep mode bit (SLP) to "1" puts the HD66766R in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD operation is completely halted. Here, all the SEG (SEG1 to SEG396) and COM (COM1 to COM176) pins output the "GND" level, resulting in no display. If the AP1-0 bits in the power control register are set to "00" in the sleep mode, the LCD drive power supply can be turned off, reducing the total current consumption of the LCD module. Table 38 Comparison of Sleep Mode and Standby Mode
Function LCD control R-C oscillation circuit Master/slave signal Sleep Mode (SLP = "1") Turned off Operates normally Operation stopped Standby Mode (STB = "1") Turned off Operation stopped Operation stopped
Standby Mode
Setting the standby mode bit (STB) to "1" puts the HD66766R in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. Specifically, all the SEG (SEG1 to SEG396) and COM (COM1 to COM176) pins for the time-sharing drive output the GND level, resulting in no display. If the AP1-0 bits are set to "00" in the standby mode, the LCD drive power supply can bet turned off. During the standby mode, no instructions can be accepted other than the start-oscillation instruction. To cancel the standby mode, issue the start-oscillation instruction to stabilize R-C oscillation before setting the STB bit to "0". When multi-chips are operated, be sure to be set to the standby mode from the slave level.
Turn off the display: D1-0 = "01" Turn off the LCD power supply: AP1-0 = "00" Set stand-by mode: STB = "1"
Stand-by mode
Issue the start-oscillation instruction Wait at least 10 ms Cancel stand-by mode: STB = "0" Turn on the LCD power supply: AP0-1 = 01/10/11 Wait at least 150 ms Turn on the display: D1-0 = "11" Procedure for Setting and Canceling Standby Mode See the power supply circuit setting.
Figure 45 Procedure for Setting and Canceling Standby Mode
63
HD66766R
Rev. 1.0-1 / September 2002
Setting flow for power supply and display instruction Power-on / off Sequence
To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system.
Power on the Vcc
1ms Power on the Reset
more than 10ms (oscillation circuit stabilization time)
Power on Initialized bits Issue use-state instruction (1) Set BS3-0 bit Set VR2-0 bit Set CT6-0 bit Set VC2-0 bit Set BT2-0 bit Set DC2-0 bit Set AP1-0 bit
Normal display
Display off sequence
more than 50ms (set-up circuit 1, 2 stabilization time)
Bits for display off
Display off Issue use-state instruction (2)
voltage polarity inverting circuit operation starting bit Set : BT3-1 = "1"
D1-0="00"
Power off setting bit
use-state instruction
Power supply circuit off control set by AP1-0
more than 200ms (set-up circuit 2 / voltage inverting circuit stabilization time)
Issue other mode setting instruction (3)
Power off the Vcc
Display on Sequence Note)
Bits for display on
Display on
D1-0="11"
Power On sequence
Power Off sequence
Figure 46 Power-on Sequence
Figure 47 Power-off Sequence
64
HD66766R
Power-off sequence
Normal case
Rev. 1.0-1 / September 2002
Turn off the display: D1-0 = 00 Issue LCD power instruction Turn off the power voltages : Vcc
To the power on sequence Emergency case Turn off the power voltage: Vcc RESET = "L" Driver SEG/COM output: GND level
To the power on sequence
Power voltage : Vcc
Vcc Turn off the power voltage GND
RESET
Vcc
RESET is input as soon as possible.
GND
Driver SEG/COM output
V1OUT
GND
Note: When hardware reset is input during the power-off period, the D1-0 bits are cleared to "00" and SEG/COM output is forcibly lowered to the GND levels.
Figure 48 Power-off sequence
65
HD66766R
Partial Sequence Setting Flow
Rev. 1.0-1 / September 2002
Normal display
Partial display
Display OFF
Display OFF D1-0 ="00"
Display OFF
Display OFF D1-0 ="00"
Power supply setting change
BT2-0 bit setting (Note) BS3-0 bit setting DC2-0 bit setting VR2-0 bit setting CT6-0 bit setting
Power supply setting change
BT2-0 bit setting (Note) BS3-0 bit setting DC2-0 bit setting VR2-0 bit setting CT6-0 bit setting
Display Duty change
NL-4-0 bit setting
Display Duty change
NL-4-0 bit setting
Frame frequency adjustment
DIV, RTN bit setting
Frame frequency adjustment
DIV, RTN bit setting
Display OFF
Display off D1-0 = "01"
Display OFF
Display off D1-0 = "01"
more than 200ms Step-up circuit output stabilizing time
Issue instruction for other mode setting
more than 200ms Step-up circuit output stabilizing time
Issue instruction for other mode setting
Display on
Display on
Display On
D1-0="11"
Display On
D1-0="11"
Partial display
Normal display
Note: Change only BT2-0 with BT3-0 = "1"
Figure 49 Normal to partial display
Figure 50 Partial to normal display
66
HD66766R
Oscillation Circuit
Rev. 1.0-1 / September 2002
The HD66766R can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. If Rf is increased or power supply voltage is decreased, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section. 1) External clock mode
Clock (264kHz) Damping resistance (2k)
OSC1 OSC2
HD66766R
2) External resistance oscillation mode
OSC1 Rf OSC2 Note: The resistance must be located near the OSC1/OSC2 pins.
HD66766R Figure 51 Oscillation Circuits The relationship between the SEG and COM output levels is as shown in the following figure. While the display is off, SEG and COM outputs go to GND level.
M VCH COM waveform
No lit
SEG waveform Lit
VS
VM VSL (GND) Lit Lit No lit No lit
VCL
Figure 52 Relationship with SEG/COM Output Level
67
HD66766R
Frame-Frequency Adjustment Function
Rev. 1.0-1 / September 2002
The HD66766R has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (DIV, RTN) during the LCD drive as the oscillation frequency is always the same. When the display duty is changed, the frame frequency can be adjusted to be the same. If the oscillation frequency is set to high, an animation or a static image can be displayed in suitable ways by changing the frame frequency. When a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. When high-speed screen switching, for an animated display, etc. is required, the frame frequency can be set high. Relationship between LCD Drive Duty and Frame Frequency The relationship between the LCD drive duty and the frame frequency is calculated by the following expression. The frame frequency can be adjusted in the retrace-line period bit (RTN) and in the operation clock division bit (DIV) by the instruction. (Formula for the frame frequency) fosc Frame frequency = Clock cycles per raster-row x division ratio x 1/duty cycle fosc: R-C oscillation frequency Duty: drive duty (NL bit) Clock cycles per raster-row: (RTN + 26) clock cycles Division ratio: DIV bit Example Calculation 1 Setting the maximum frame frequency to 60 Hz [Hz]
Display duty: 1/176 Retrace-line period: 0 clock (RTN3-0 = "0000") Operation clock division ratio: 1 division fosc = 60 Hz x (0 + 26) clock x 1 division x 176 lines = 275 (kHz) In this case, the R-C oscillation frequency becomes 275 kHz. The external resistance value of the R-C oscillator must be adjusted to be 275 kHz. The display duty can be changed by the partial display, etc. and the frame frequency can be the same by setting the RNT bit and DIV bit to achieve the following. (Partial display): Display duty: 1/40 Retrace-line period: 1 clock (RTN3-0 = "0002") Operation clock division ratio: 3 division Frame frequency = 275 kHz/ ((3 + 26) clock x 4 division x 40 lines) = 59.2 (Hz) Example Calculation 2 Switching the frame frequency to suit animation/static image display
(Animation display): Frame frequency: 90 Hz Display duty: 1/176 Retrace-line period: 0 clock (RTN3-0 = "0000") Operation clock division ratio: 1 division fosc = 90 Hz x (0 + 26) clock x 1 division x 176 lines = 412 (kHz) (Static image display): Frame frequency: 90 Hz Display duty: 1/176 Retrace-line period: 1 clock (RTN3-0 = "1101") Operation clock division ratio: 1 division Frame frequency: 412 kHz/ ((13 + 26) clock x 1 division x 176 lines) = 60.0 (Hz)
68
HD66766R
n-raster-row Reversed AC Drive
Rev. 1.0-1 / September 2002
The HD66766R supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 rasterrows (C-pattern waveform). When a problem affecting display quality occurs, such as cross-talk at high-duty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality. Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in the LCD cells.
1 frame
175176 1 2 3 4 5 6
1 frame
175176 1 2 3
1234
56
7 8 9 10 11 12 13
7 8 9 10 11 12 13
B-pattern waveform drive -1/176 duty
C-pattern -wave form drive - 1/176 duty - 11 raster-row reversal - Without EORs
C-pattern waveform drive - 1/176 duty - 11 raster-row reversal - With EORs
Notice : Specify the number of AC drive raster-rows and the necessity of EOR so that the DC bias is not generated to the LCD.
Figure 53 Example of an AC Signal under n-raster-row Reversed AC Drive
69
HD66766R
Screen-division Driving Function
Rev. 1.0-1 / September 2002
The HD66766R can select and drive two screens at any position with the screen-driving position registers (R14h and R15h). Any two screens required for display are selectively driven and a duty ratio is lowered by LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption. For the 1st division screen, start line (SS17-10) and end line (SE17-10) are specified by the 1st screen-driving position register (R14h). For the 2nd division screen, start line (SS27-20) and end line (SE27-20) are specified by the 2nd screen-driving position register (R15h). The 2nd screen control is effective when the SPT bit is "1". The total count of selection-driving lines for the 1st and 2nd screens must correspond to the LCD-driving duty set value.
1/24 duty driving on 2 screen
COM1 COM7
1st screen: 7 raster-row driving Always applying non-selection level 2nd screen: 17 raster-row driving
COM26
COM42
Always applying non-selection level
-Driving duty: NL4-0 = "00010" (1/24 duty) -1st screen setting: SS17-10 = "00"H, SE17-10 = "06" H -2nd screen setting: SS27-20 = "19"H, SE27-20 = "29" H, SPT = "1"
Figure 54 Display example in 2-screen division driving
70
HD66766R
Rev. 1.0-1 / September 2002
Restrictions on the 1st/2nd Screen Driving Position Register Settings
The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10) of the 1st screen driving position register (R14h) and the start line (SS27-20) and end line (SE27-20) of the 2nd screen driving position register (R15h) for the HD66766R. Note that incorrect display may occur if the restrictions are not satisfied. Table 39 Restrictions on the 1st/2nd Screen Driving Position Register Settings
1st Screen Driving (SPT = 0) SS17-10 SE17-0 "AF"H * Time-sharing driving for COM pins (SS1+1) to (SE1+1) * Non-selection level driving for others 2nd Screen Driving (SPT = 1) SS17-10 SE17-10 < SS27-20 SE27-20 "AF"H * Time-sharing driving for COM pins (SS1+1) to (SE1+1) and (SS2+1) to (SE2+1) * Non-selection level driving for others
Register setting
Display operation
Notes: 1. When the total line count in screen division driving settings is less than the duty setting, non-selection level driving is performed without the screen division driving setting range. 2. When the total line count in screen division driving settings is larger than the duty setting, the start line, the duty-setting line and the lines between them are displayed and non-selection level driving is performed for other lines. 3. For the 1st screen driving, the SS27-20 and SE27-20 settings are ignored.
71
HD66766R
LCD Voltage Generation Circuit
Rev. 1.0-1 / September 2002
Figure 58 shows a configuration of the HD66766R LCD drive voltage generation circuit. It consists of step-up circuit 1 that doubles or triples the voltage that is applied to Vci1, step-up circuit 2 that multiplies the voltage from step-up circuit 1 by two to five times, and polarity circuit that generates a VCL level by inverting the VCH level centered around the VM level. These circuits generate VCH and VCL that are power supply for COM outputs. The LCD driving level for SEG outputs (VSH and VM) are generated by dividing resistance at the VREF level.
Vcc + VREFL VREF Control Amplifier BIASC bias amplifier + -
+ -
Vci2
1.0F
bias control VREFM Vcc 1.0F VciOUT Vci Control Circuits Vci1 1.0F C11C11+ 1.0 F C12C12+ VOUT 1.0F VOUT generator Step - up circuits 1 VCH Generator Step - up circuits 2
C21C21+ C22C22+ C23C23+ C24C24+ VCH *
1.0F
1.0F
1.0F
1.0F
1.0F
Contrast control
+ + -
VSH
1.0F 1.0M
VM
1.0F
AVcc Vcc GND AGND
SEG driver
VCL
1.0F * Shot-key barrier diode
COM driver
HD66766R
VCL generator Polarity inverting circuit
CEM * CEP 0.47uF
Note:
Figure 55 Configuration of internal power circuit
1) Use condenser with character B. 2) Condensers with asterisk (*) need resist pressure more than 25V. 3) Insert shot-key barrier diode. (VF = 0.6V / 20mA, VR>=30V)
72
HD66766R
Rev. 1.0-1 / September 2002
Notes: 1. Generate an output voltage (VOUT) from step-up circuit 1 within the range from 4.0 to 5.75V. 2. Do not allow the output voltage (VCH) from step-up circuit 2 to exceed 22 V. 3. Do not allow the output from Vci2 to exceed VOUT voltage . 4. When capacitor with polarity is used, be sure that an inverted voltage is not applied to it in any state of the system. 5. Vci1 is used as both the reference voltage input and power supply in the step-up circuit. Keep sufficient LCD drive current. 6. Rated voltage of capacitors possible to be used are as described below. Required voltage depends on used panels. When actual voltage is less than 16V, capacitors with 16V rated voltage can be used. 6.3V: VREFM, VciOUT, C11, C12, VOUT, BIASC, Vci2, C21, C22, C23, VSH, VM 25V(16V): VCH, CE, VCL LCD Drive Voltage The required voltage can be calculated by applying the following expressions. standard; generate a voltage to suit the panel to be used. VSH-VM, VM-VSL 1 2 1 VCH-VM, VM-VCL LCD Drive Bias An optimal bias can be calculated by applying the following expression. The value that has been calculated is theoretically optimal. If a lower bias value than the optimal value is used to drive the LCD, contrast may be reduced depending on lighting conditions. However, the power consumption can be reduced by lowering the drive voltage. Adjust the value according to the system to be used.
Bias value = 2N N
Drive voltages are
x Vth
-1 -1
x Vth
Vth: Threshold voltage of the LCD panel to be used. N: Display duty cycle.
2N N N
2
1
N
How to determine the VCH voltage VCH = NB x ND2 x VSH NB : Bias ratio ND2 : Step-up factor of the step-up circuit 2 Contrast adjustment RB : Contrast resistance (0.000R to 1.016R) VSH = VREFM x 2R / (Rb + 2R) Table 40
CT setting value CT6 0 0 0 0 0 CT5 0 0 0 0 0 CT4 0 0 0 0 0 CT3 0 0 0 0 0 CT2 0 0 0 0 1 CT1 0 0 1 1 0 CT0 0 1 0 1 0 Rb resist value
VCI2
step-up circuit 2
VCH
VCI2=VM*~ B N VCH=VM*~NB *~Nc2
VREFM
Rb
1.016R 1.008R 1.000R 0.992R 0.984R
Rb*F Resist for adjusting contrast (0.000R*1.016R) VSH
R VM R
1 1
1 1
1 1
1 1
1 1
1 1
0 1
0.008R 0.000R
VSL
Figrue 56 73
HD66766R
How to determine the power setting value 1. Determine LCD drive bias
Rev. 1.0-1 / September 2002
Determine LCD drive bias first. LCD drive bias is theoretically (1/SQRT (display duty)) optimal; however, the total drive voltage can be reduced by lowering bias ratio. Consider the display quality, the drive voltage and the current consumption. 2. Determine VOUT voltage Determine factor of Vc1 regulator and step-up factor so as to set output voltage, VOUT of step-up circuit 1 4.0 to 5.75V, setting input voltage Vci2 of step-up circuit 2 more than +0.5V. Since the entire electric power for driving LCD is supplied from step-up circuit, subsequent voltage fall need to be considered. 3. Segment drive voltage calculation Segment output drive voltage is calculated by the following expression. Vseg = 2xB
(B-1)
x VTH
B
: LCD drive bias ratio
Vth: LCD threshold voltage 4. Common drive voltage calculation Common output drive voltage is calculated by the following expression. Vcom =
Vseg 2
x (B+1) B : LCD drive bias ratio
5. Determine input voltage of step-up circuit 2 Determine input voltage of step-up circuit 2. This voltage is determined by dividing Vcom voltage by step-up factor; lower factors are used for low current consumption. Vci2 voltage need to be less than VOUT voltage (4.0 to 5.75 V)- 0.5V. Example of register setting on power supply Examples of register setting values on power supply are described below. Example 1: 1/176 duty ratio, Vcc = VREFL = 3.0V, 1/13 bias BS3-0 = H'8 BT2-0 = H'4 BT3 = H'1 DC2-0 = H'6 TBD AP1-0 = H'1 VC2-0 = H'0 VR2-0 = H'0 CT6-0 : bias adjustment 1.4 times : step-up circuit 1 2 times step-up circuit 2 5 times
: operate voltage inverting circuit step-up circuit 1 frequency 32 clocks step-up circuit 2 frequency 128 clocks : low fixed current in the amplifier : Vci1 = 0.92 x Vcc = 2.75V : VREFM = 1.1 x VREFL : appropriate contrast setting values
74
HD66766R
Rev. 1.0-1 / September 2002
Example 2: 1/176 duty ratio, Vcc = VREFL = 2.4V, Vci = 2.8V, 1/13 bias BS2-0 = H'8 BT2-0 = H'4 BT3 = H'1 : bias adjustment 1.4 times : step-up circuit 1 2 times step-up circuit 2 5 times
: operate voltage inverting circuit : step-up circuit 1 frequency 32 clocks step-up circuit 2 frequency 128 clocks
DC2-0 = H'6 TBD AP1-0 = H'1 VC2-0 = H'4 VR3-0 = H'2 CT6-0
: low fixed current in the amplifier : internal Vci1 regulator off : VREFM = 1.4 x VREFL : appropriate contrast setting values 2.8V directly supplied to Vci1
Example 3: Partial display, 1/24 duty ratio, Vcc = 2.4V, Vci = 2.8V, 1/4 bias BS2-0 = H'0 BT2-0 = H'0 BT3 = H'1 : bias adjustment 1.25 times : step-up circuit 1 2 times step-up circuit 2 2 times
: operate voltage inverting circuit : step-up circuit 1 frequency 64 clocks step-up circuit 2 frequency 128 clocks
DC2-0 = H'6 TBD AP1-0 = H'1 VC2-0 = H'4 VR3-0 = H'2 CT6-0
: low fixed current in the amplifier : internal Vci1 regulator off : VREG 1 = 1.4 x VREFL : appropriate contrast setting values
75
HD66766R
HD66766R power supply level correlation
Rev. 1.0-1 / September 2002
VCH
BT2-1 (2 to 5 times) VC2-0 CT6-0 (contrast adjustment) Vci2 BT0 (2 to 3 times)
VOUT (4.0 to 5.75 V) VREFM ( VOUT)
(0.92 to 0.68 times)
Vcc Vci1
VREFL ( VCC)
GND
VR2-0 (1.1 to 3.4 times)
VSH VM GND
BS3-0 (0.5 to 2.165 times)
Voltage polarity inversion between VCH and VM
VCL Figure 57 HD66766R Power supply level correlation
76
HD66766R
Rev. 1.0-1 / September 2002
Connection of condenser related to the magnification of step up circuit 1
(1) 2 times step-up circuit 1.0 uF VciOUT Vci1 C111.0 u F C11+ 1.0 u F C12C12+ 1.0 uF VOUT 1.0u F VOUT
VOUT generating step-up circuit 1
(2 Vci1) x
u adjusting circuit
(2) 3 times step-up circuit (3 x Vci1) 1.0 uF VciOUT Vci1 C11C11+ 1.0 uF C12C12+
VOUT generating step-up circuit 1 u adjusting circuit
Figure 58
Figure 59
Connection of condenser related to the magnification of step up circuit 2
(1) 2 times step-up circuit (2 x Vci2)
Vci2 C21C21+ C22VCH generating step-up circuit 2 C22+ C23C23+ C24C24+ 1.0 uF VCH 1.0 uF VCH generating step-up circuit 2 1.0 uF
(2) 3 times step-up circuit (3 x Vci2)
Vci2 C21C21+ C22C22+ C23C23+ C24C24+ 1.0 uF VCH 1.0 uF 1.0 uF 1.0 uF
Figure 60
(3) 4times step-up circuit (4 x Vci2)
Vci2 C21C21+ C22VCH generating step-up circuit 2 C22+ C23C23+ C24C24+ VCH 1.0 uF 1.0 uF 1.0uF 1.0 uF
Figure 61
(4) 5times step-up circuit (5 x Vci2)
Vci2 1.0 uF C21C21+ C22VCH generating step-up circuit 2 C22+ C23C23+ C24C24+ VCH 1.0 uF 1.0 uF 1.0 uF 1.0uF 1.0 uF
1.0 uF
Figure 62
Figure 63
77
HD66766R
Absolute Maximum Ratings Table 41 Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Input voltage Operating temperature Storage temperature Symbol Vcc Vcil VCH -VCL Vt Topr Tstg Unit V V V V C C
Rev. 1.0-1 / September 2002
Value -0.3 to + 4.6 -0.3 to + 4.6 -0.3 to + 46 -0.3 to Vcc + 0.3 -40 to + 85 -55 to + 110
Notes* 1, 2 1, 3 1, 4 1 1, 5 1
Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limit is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 2. Vcc GND must be maintained 3. Vcil GND must be maintained. 4. VCH GND must be maintained GND VCL must be maintained 5. For die and wafer products, specified up to 85 C.
78
HD66766R
Table 42
Item Input high voltage Input low voltage Output high voltage (1) (DB0-15 pins) Output low voltage (1) (DB0-15 pins) Symbol Unit Test Condition VIH VIL VOH1 V V V VCC = 2.2 to 3.6 V VCC = 2.2 to 3.6 V IOH = -0.1 mA VCC = 2.2 to 2.4 V, IOL = 0.1 mA VCC = 2.4 to 3.6 V, IOL = 0.1 mA Driver ON resistance
(SEG pins)
Rev. 1.0-1 / September 2002
DC Characteristics (VCC = 2.2 to 3.6 V, VCH-VCL=8V to 44V, Ta = -40 to +85C*1)
Min 0.7 VCC -0.3 Typ -- -- Max VCC 0.15VCC -- 0.2 VCC 0.15VCC 3 3 1 600 Notes 2, 3 2, 3 2 2 2 4 4 5 6
0.75VCC -- -- -- -- -- -1 -- -- 0.35 0.90 -- 480.
VOL1
V
RSEG RCOM ILi IOP
k k A A
Id = 0.05 mA, VLCD = 3 V Id = 0.05 mA, VCH - VCL = 44 V Vin = 0 to VCC
Driver ON resistance
(COM pins)
I/O leakage current Current consumption during normal operation (VCC - GND)
Current consumption during standby mode (VCC - GND) VREFL input voltage VREFM output voltage Step up circuit 1 output voltage Step up circuit 2 output voltage
IST
A
-- R-C oscillation VCC = 3.0 V, VCH = 20V, VM = 1.6V, VCL = -16.8V,Ta = 25C fOSC = 276 Khz (1/176 duty), 1/12 Bias CT minimum AP minimum, display all 0 Step-up 1 = two times Step-up 2 = five times VCI1 = 0.92 x VCC VCC = 3 V, Ta = 25C -- Vcc = 3V, Ta = 85C -- -- -- 4.0 --
0.1 -- -- -- -- --
5 50 Vcc VOUT -0.5 5.75 VOUT - 0.5
VREFL V VREFM V VOUT VCI2 V V
Vcc = 2.2V 3.6V VOUT = 4.0V 5.75V
79
HD66766R
Step up circuit characteristics
Table 43
Item Terminal Unit Test Condition
Rev. 1.0-1 / September 2002
Min
Typ
Max
Notes
Step up circuit 1
VOUT
V
Step up circuit 2
VCH
V
Step up circuit 3
VCL
V
VCC = 3.0 [V] Vci step up factor = 0.92 Step up factor : two times 5.25 Step up cycle: 32 divided cycle Load voltage = 400 [A] VCC = 3.0 [V] VOUT = 5.5 [V] VREFL = 3.0 [V] VREFM = 1.1 x VREFL Constant current of operation amplifier: small 21.2 Contrast adjustment value = 0.000R 1/12 bias Step up cycle of step up circuit 2: 96 divided cycle Step up factor: Five times Load current = 20 [uA] VCC = 3.0 [V] VOUT = 5.5 [V] VREFL = 3.0 [V] VREFM = 1.1 x VREFL Constant current of operation amplifier: small -21.0 Contrast adjustment value = 0.000R 1/12 bias Step up cycle of polarity inversion circuit: 96 divided cycle Step up factor: Five times Load current = 20 [uA]
5.48
--
--
21.3
--
(9)
-21.2
--
(9)
80
HD66766R
Rev. 1.0-1 / September 2002
AC Characteristics (VCC = 2.2 to 3.6 V, Ta = -40 to +85C*1)
Table 44 Clock Characteristics (VCC = 2.2 to 3.6 V)
Item External clock frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock Symbol fcp Duty trcp tfcp fOSC Unit kHz % s s kHz Test Condition VCC = 2.2 to 3.6 V VCC = 2.2 to 3.6 V VCC = 2.2 to 3.6 V VCC = 2.2 to 3.6 V Rf = 200k, VCC = 3 V Min 151 45 -- -- 220 Typ 275 50 -- -- 275 Max 640 55 0.2 0.2 330 Notes 7 7 7 7 8
68-system Bus Interface Timing Characteristics Table 45 Normal Write Mode (HWM=0) (Vcc = 2.2 to 2.4 V)
Item Enable cycle time Enable high-level pulse width Enable low-level pulse width Enable rise/fall time Set up time (RS, R/W to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Write Read Write Read Symbol tCYCE tCYCE PWEH PWEH PWEL PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE tDHRE Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 600 800 90 350 300 400 -- 10 5 60 15 -- 5 Min -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 25 -- -- -- -- 200 -- Max
Table 46 High-Speed Write Mode (HWM=1)
(Vcc = 2.2 to 2.4 V) Item Enable cycle time Enable high-level pulse width Enable low-level pulse width Enable rise/fall time Set up time (RS, R/W to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Write Read Write Read Symbol tCYCE tCYCE PWEH PWEH PWEL PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE tDHRE Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Min Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 200 800 90 350 90 400 -- 10 5 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
81
HD66766R
Normal Write Mode (HWM=0) Table 47 (Vcc = 2.4 to 3.6 V)
Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Set up time (RS, R/W to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol tCYCE tCYCE PWEH PWEH PWEL PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE tDHRE Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev. 1.0-1 / September 2002
Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1
Min 200 300 40 150 100 100 -- 10 0 2 60 2 -- 5
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 --
Note -- -- -- -- -- -- -- Using status read Not using status read -- -- -- -- --
High-Speed Write Mode (HWM=1)
Table 48 (Vcc = 2.4 V to 3.6 V) Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Set up time (RS, R/W to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Symbol tCYCE tCYCE PWEH PWEH PWEL PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE Unit ns ns ns ns ns ns ns ns ns ns ns ns Test Min Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 100 300 40 150 40 100 -- 10 0 2 60 2 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 Note -- -- -- -- -- -- -- Using status read Not using status read -- -- -- --
82
HD66766R
80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) Table 49 (Vcc = 2.2 to 2.4 V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time tAH tDSW tH tDDR tDHR ns ns ns ns ns Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS Unit ns ns ns ns ns ns ns ns
Rev. 1.0-1 / September 2002
Test Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Min 600 800 90 350 300 400 -- 10 5 60 15 -- 5
Typ -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
High-Speed Write Mode (HWM=1) Table 50 (Vcc = 2.2 to 2.4 V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time tAH tDSW tH tDDR tDHR ns ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 5 60 15 -- 5 -- -- -- -- -- -- -- -- 200 -- Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS Unit ns ns ns ns ns ns ns ns Test Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 200 800 90 350 90 400 -- 10 Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 --
83
HD66766R
Normal Write Mode (HWM = 0) Table 51 (Vcc = 2.4 to 3.6 V)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS tAH tDSW tH tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev. 1.0-1 / September 2002
Test Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Min 200 300 40 150 100 100 -- 10 0 2 60 2 -- 5
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 --
Note
Using status read Not using status read
High-Speed Write Mode (HWM=1)
Table 52 (Vcc = 2.4 to 3.6 V) Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high -level pulse width Read high -level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol tCYCW tCYCR PWLw PWLR PWHW PWHR t WRr, WRf tAS tAH tDSW tH tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Min Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 100 300 40 150 40 100 -- 10 0 2 60 2 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 -- Using status read Not using status read Note
84
HD66766R
Rev. 1.0-1 / September 2002
Clock Synchronized Serial Interface Timing Characteristics Table 53 (Vcc = 2.2 to 2.4 V)
Item Write (received) Read (transmitted) Write (received) Read (transmitted) Write (received) Symbol Unit Test Condition Min Typ Max
tSCYC tSCYC tSCH tSCH tSCL tSCL tscr, scf tCSU tCH tSISU tSIH tSOD tSOH
us us ns ns ns ns ns ns ns ns ns ns ns
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
0.1 0.25 40 120 40 120 -- 20 60 30 30 -- 5
-- -- -- -- -- -- -- -- -- -- -- -- --
20 20 -- -- -- -- 20 -- -- -- -- 130 --
Serial clock cycle time
Serial clock high-level pulse width
Serial clock low-level pulse width
Read (transmitted) Serial clock rise/fall time Chip select set up time Chip select hold time
Serial input data set up time Serial input data hold time Serial input data delay time Serial input data hold time
Table 54 (Vcc = 2.4 to 3.6 V)
Item Write (received) Read (transmitted) Symbol Unit Test Condition Min Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max
tSCYC tSCYC tSCH tSCH tSCL tSCL tscr, scf tCSU tCH tSISU tSIH tSOD tSOH
us us ns ns ns ns ns ns ns ns ns ns ns
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
0.076 0.15 40 70 35 70 -- 20 60 30 30 -- 5
20 20 -- -- -- -- 20 -- -- -- -- 130
--
Serial clock cycle time
Write (received) Serial clock high-level pulse width Read (transmitted) Write (received) Read (transmitted)
Serial clock low-level pulse width
Serial clock rise/fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time
85
HD66766R
Reset Timing Characteristics (VCC = 2.2 to 3.6 V) Table 55
Item Reset low-level width Reset rise time Symbol tRES trRES Unit ms ms Test Condition Figure 4 Figure 4
Rev. 1.0-1 / September 2002
Min 1 --
Typ -- --
Max -- 10
Electrical Characteristics Notes
1. For bare die and wafer products, specified up to 85C. 2. The following three circuits are I pin, I/O pin, O pin configurations.
Pins: RESET*, CS*, E/WR, RW/RD, RS, OSC1, IM2-1, IM0/ID, TEST1, TEST2 Vcc PMOS NMOS GND Pins: OSC2
Vcc PMOS
NMOS GND
Figure 64
Pins: DB15 -DB2, DB1/SD0, DB0/SD1 Vcc PMOS
Figure 65
(Input circuit)
NMOS Vcc PMOS
(Tri-state output circuit)
Output enable Output data
NMOS GND
Figure 66 I/O Pin Configuration 3. The TEST1, TEST2 pins must be grounded and the IM2/1 and IM0/ID pins must be grounded or connected to Vcc. 4. Applies to the resistor value (RSEG) between VSH, GND pins and segment signal pins. 5. This excludes the current flowing through output drive MOSs.
86
HD66766R
Rev. 1.0-1 / September 2002
6. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. Even if the CS pin is low or high when an access with the interface pin is not performed, current consumption does not change. 7. Applies to the external clock input (figure ). Th Tl Th Th+ Tl x 100%
2k
Oscillator
OSC1 Open OSC2
0.7Vcc 0.5Vcc 0.3Vcc t rcp t fcp
Duty =
Figure 67 External Clock Supply 8. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table). 9. Set VCI2 to maintain the relation VCI2 =< VOUT-0.5V.
OSC1 Rf OSC2 Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
Figure 68 Internal Oscillation
External Resistance (Rf) 75 k 130 k 180 k 200 k 240 k 280 k 360 k 470 k Vcc = 1.8V 364 263 210 193 174 156 129 102 R-C Oscillation Frequency: fosc Vcc = 2.2 V 495 345 270 245 218 194 158 122 Vcc = 2.4 V 559 381 295 266 Vcc = 3.0 V 631 421 323 290 256 226 182 137 Vcc = 3.6 V 687 453 344 307 270 238 191 142
236
210 170 129
Table 56 External Resistance Value and R-C Oscillation Frequency (Referential Data)
87
HD66766R
Step-up circuit loading characteristics
(1) Step-up circuit 1 - loading characteristic
Rev. 1.0-1 / September 2002
(Reference data)
Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] (2) Vci1 step-up magnification = 0.92, Step-up magnification two times 5.5 5.0 VOUT [V] 4.5 4.0 3.5 3.0 0 300 600 900 Load voltage [uA] 1200 1500
32 divided frequency 64 divided frequency
Figure 69 Step-up circuit 1- load characteristic (AP=01 amplifier constant voltage: small)
5.5 5.0 VOUT [V] 4.5 4.0 3.5 3.0 0 300 600 900 1200 1500
32 divided frequency 64 divided frequency
Load voltage [uA] Figure 70 Step-up circuit 1- load characteristic (AP=10 amplifier constant voltage: medium) 5.5 5.0 VOUT [V] 4.5 4.0 3.5 3.0 0 300 600 900 1200 1500
32 divided frequency 64 divided frequency
Load voltage [uA] Figure 71 Step-up circuit 1- load characteristic (AP=11 amplifier constant voltage: large)
88
HD66766R
(2) Step-up circuit 2 - loading characteristic
Rev. 1.0-1 / September 2002
Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] Vci1 step-up magnification = 0.92, Step-up circuit 1: step-up magnification two times 32 divided frequency, VREFM = 1.1 x VREFL, CT = 0.00R1/12 Bias Step-up circuit 2: Five times step-up 21.6 21.5 VCH [V] 21.4 21.3 21.2
128 divided frequency 32 divided frequency 64 divided frequency 96 divided frequency
21.1 0 10 20 30 40 50 Load voltage [uA] Figure 72 Step-up circuit 2- load characteristic (AP=01 amplifier constant voltage: small)
21.6 21.5 VCH [V] 21.4 21.3 21.2 21.1 0 10 20 30 40 50
32 divided frequency 64 divided frequency 96 divided frequency 128 divided frequency
Load voltage [uA] Figure 73 Step-up circuit 2- load characteristic (AP=10 amplifier constant voltage: medium)
21.6 21.5 VCH [V] 21.4 21.3
128 divided frequency 32 divided frequency 64 divided frequency 96 divided frequency
21.2 21.1 0 10 20 30 40 50 Load voltage [uA] Figure 74 Step-up circuit 2- load characteristic (AP=11 amplifier constant voltage: large)
89
HD66766R
(3) Polarity inversion circuit - loading characteristic
Rev. 1.0-1 / September 2002
Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] Vci1 step-up magnification = 0.92, Step-up circuit 1 step-up magnification two times 32 divided frequency, VREFM = 1.1 x VREFL, CT = 0.00R 1/12 Vias Step-up circuit 2: Five times 21.5 21.3 VCL [V] 21.1 20.9 20.7
128 divided frequency 32 divided frequency 64 divided frequency 96 divided frequency
20.5 0 10 20 30 40 50 Load voltage [uA] Figure 75 Polarity inversion circuit - Load characteristic (AP=01 amplifier constant current: small) 21.5 21.3 VCL [V] 21.1 20.9 20.7 20.5 0 10 20 30 Load voltage [uA] 40 50
32 divided frequency 64 divided frequency 96 divided frequency 128 divided frequency
Figure 76 Polarity inversion circuit - Load characteristic (AP=10 amplifier constant current: medium)
21.5 21.3 VCL [V] 21.1 20.9 20.7 20.5 0 10 20 30 Load voltage [uA] 40 50
32 divided frequency 64 divided frequency 96 divided frequency 128 divided frequency
Figure 77 Polarity inversion circuit - Load characteristic (AP=11 amplifier constant current: large)
90
HD66766R
Load Circuits
AC Characteristics Test Load Circuits
Rev. 1.0-1 / September 2002
Data bus: DB15 to DB0 Test point
50pF
Figure 78 Load Circuit
91
HD66766R
Timing Characteristics
68-system Bus Operation
Rev. 1.0-1 / September 2002
RS R/W
VIH VIL tASE
VIH VIL tAHE
CS*
VIL Note 1) PWEH VIH VIH VIL
VIL PWEL
E VIL VIL
tEr
tEf t DSWE tCYCE tHE
VIH VIL tDHRE VOH1 VOL1 Read data VOH1 VOL1
Note2)
DB0 to DB15
tDDRE
VIH VIL
Wrire data
Note 2) DB0 to DB15
Figure79 68-system Bus Timing
Notes: 1) PWEH is specified in the overlapped period when CS* is low and E is high. 2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND.
92
HD66766R
80-system Bus Operation
Rev. 1.0-1 / September 2002
RS
VIH VIL
tAS
VIH VIL
tAH
VIH CS* VIL
Note 1) PWLW, PWLR WR * RD* PWHW, PWHR
VIH VIL tWRr VIL tWRf
VIH
tCYCW, tCYCR
tDSW DB0 to DB15
tDDR
tHWR VIH VIL
tDHR
VIH VIL
Wrire data
DB0 to DB15
VOH1 Read data VOL1
VOH1 VOL1
Figure 80 80-system Bus Timing Note1) PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is low. Note2) Parallel data transfer is enabled on the DB15-0 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND.
93
HD66766R
Clock Synchronized Serial Interface Operation
Rev. 1.0-1 / September 2002
Start: S
CS* VIL tSCYC tscf tSCH SCL VIH VIL tSISU SDI VIH VIL tSOD SDO VOH1 VOL1 Output data tSIH Input data VIH VIL Input data VIL VIH VIH VIL tSCL VIH VIL
End: P
VIH VIL
tCSU
tscr
tCH
tSOH VOH1 VOL1
Output data
Figure 81 Clock Synchronized Serial Interface Timing
Reset Operation
trRES tRES VIH RESET* VIL VIL Figure 82 Reset Timin
94
HD66766R
Additional Issue
Rev. 1.0-1 / September 2002
HD66766R Contrast fluctuation on RAM access
Hitachi one-chip driver; HD66766R has contrast fluctuation while accessing the internal RAM. This phenomenon occurs according to the structure of external circuit and the usage of HD66766R. Please have a clear understanding of the phenomenon and measures described below before using HD66766R.
1. Contrast fluctuation
When HD66766R is mounted on glass, the grand terminal gets contact with resistance of ITO wiring. HD66766R has 8 GNDs, 4 AGNDs for power supply circuit, and another 4 GNDs for RAM and Logic. When all the GNDs are connected on glass with ITO, transferring display data to the internal RAM at high-speed causes high current consumption. And resistance of ITO wiring connected with GND terminal raises the voltage. The raised voltage is amplified with a step-up circuit, and it results in a decrease of VCH/VCL voltage causing contrast fluctuation on display. Figure 1 shows the mechanism of the phenomenon. Figure 2 shows decrease of VCH voltage according to RAM access frequency and resistance of ITO wiring. (The value shown in Figure 2 is the actual data of a typical sample of HD66766R measured by Hitachi's jig.)
2. Measures
ITO patterns on glass must be separated as shown in Figure 3. (Even if GND bumps are separated on LSI, if ITO patterns on glass are connected, GND level rises up in RAM circuit and Logic circuit.) Also, GND resistor should be designed to be less than 10 , considering the decrease of VCH voltage caused by the raise of GND voltage.
LCD
HD66766R RAM Voltage decrease Voltage generating circuit VCH Voltage decrease
RAM access current GND
Resistance of ITO wiring
Figure 1 Influence of ITO wiring resistance
95
HD66766R
0.6 VCH Voltage decrease (V) 0.5 0.4 0.3 0.2 0.1 0 0 5 10
Rev. 1.0-1 / September 2002
RAM access frequency
1MHz 2MHz 3MHz 4MHz
15
Resistance of ITO wiring () Figure 2 VCH voltage decrease depending on RAM access frequency and Resistance of ITO wiring
Power Supply Circuit Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc AGND AGND GND
RAM, LOGIC GND GND GND
Power Supply Circuit AGND AGND RESET2*
ITO
ITO
ITO
ITO
Slit Figure 3 Recommended ITO Connection Pattern (HCD667X66)
Power Supply Circuit Vcc Vcc Vcc Vcc AVcc AVcc AVcc AVcc AGND AGND GND
RAM, LOGIC GND GND GND
Power Supply Circuit AGND AGND RESET2*
ITO
ITO
ITO
ITO
ITO
Slit Figure 4 Recommended ITO Connection Pattern (HCD667X66R)
96
HD66766R
Maintenance history report Rev. 1.0 1.1 Date August 8, 2002 September 17, 2002
Rev. 1.0-1 / September 2002
Contents First release P74 2.Determine VOUT voltage Line2 From "4.0 to 5.5V" to "4.0 to 5.75 V" P74 5.Determine input voltage of step-up circuit2 Line 3 From "4.5 to 5.75V)-0.5V" to " (4.0 to 5.75V)-0.5V
97

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